preprints.org > engineering > electrical and electronic engineering > doi: 10.20944/preprints202301.0056.v1

Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Version 1 : Received: 31 December 2022 / Approved: 4 January 2023 / Online: 4 January 2023 (03:27:44 CET)

This paper introduces a novel 3D NoC router that combines buffered and bufferless routing with approximate priority comparison when deflecting flits. Our proposal is a modification of an asymmetrical router that is buffered in the z dimension ports and bufferless in the x and y dimension ports. Flits that request output ports in the x and y dimensions are granted or deflected based on approximate, instead of accurate, priority comparison. Experimental results show that the proposed router, besides effectively combining the advantages of both buffered and bufferless routers, it achieves additional performance and area gains due to the reduced logic required for approximate priority comparison in flit deflections. Experimental results using synthetic and realistic traffic show that the proposed router begins to saturate at a sifnificantly higher injection rate than a bufferless router, but at a slightly lower injection rate than when using accurate priority comparison. Furthermore, the proposed router achieves higher clock frequencies and reduced area compared to the simpler permutation network.

3D Networks-on-Chip; NoC; bufferless routing; approximate computing

Engineering, Electrical and Electronic Engineering

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