Preprint Review Version 1 Preserved in Portico This version is not peer-reviewed

Fabrication Methods for Integrating 2D Materials

Version 1 : Received: 18 November 2021 / Approved: 18 November 2021 / Online: 18 November 2021 (15:00:46 CET)

How to cite: Moss, D. Fabrication Methods for Integrating 2D Materials. Preprints 2021, 2021110334 (doi: 10.20944/preprints202111.0334.v1). Moss, D. Fabrication Methods for Integrating 2D Materials. Preprints 2021, 2021110334 (doi: 10.20944/preprints202111.0334.v1).

Abstract

With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.

Keywords

2D materials; integrated devices; fabrication techniques; heterostructures

Subject

ENGINEERING, Electrical & Electronic Engineering

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