Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array

Francisco Bilendo; Sheng Shouzhao

doi:10.20944/preprints201807.0590.v1

Preprint Brief Report Version 1 Preserved in Portico This version is not peer-reviewed

Version 1 : Received: 30 July 2018 / Approved: 30 July 2018 / Online: 30 July 2018 (14:45:25 CEST)

Abstract— Flight Control System is an integrated avionics system equipped with the minimum required components for an autonomous flight. This paper focuses on the Hardware Design of the Flight Control System and presents specific details of the components and its interface. The system architecture is based on Field Programmable Gate Array and Digital Signal Processor. Employing these two processors in the flight control system would improve the Flight Control System performance in terms of fast sequential processing of high-level control algorithms. In addition to Field Programmable Gate Array and Digital Signal Processor, the flight control computer system will also make use of Global Positioning System and Micro Electro Mechanical System sensors. The project will be implemented using Altera’s System On Programmable Chip builder, currently known as Qsys – Platform Designer implemented in Quartus-II. The system employs Nios-II processor which is 32-bit soft-core embedded-processor architecture designed especially for the Altera’s family of Field Programmable Gate Array. From conceptualization to final design, this paper presents the functionality of the different modulus and complex interfaces employed in this Flight Control System.

Field Programmable Gate Array, Flight Control System, and Hardware Design.

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Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array

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