Preprint Article Version 1 This version is not peer-reviewed

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS-NEM Hybrid Circuits

Version 1 : Received: 30 May 2018 / Approved: 30 May 2018 / Online: 30 May 2018 (16:27:49 CEST)
Version 2 : Received: 29 June 2018 / Approved: 29 June 2018 / Online: 29 June 2018 (16:36:01 CEST)

A peer-reviewed article of this Preprint also exists.

Jo, H.C.; Choi, W.Y. Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS–NEM Hybrid Circuits. Micromachines 2018, 9, 317. Jo, H.C.; Choi, W.Y. Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS–NEM Hybrid Circuits. Micromachines 2018, 9, 317.

Journal reference: Micromachines 2018, 9, 317
DOI: 10.3390/mi9070317

Abstract

Considering the isotropic release process of nanoelectromechanical systems (NEMS), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS-NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from vapor hydrogen fluoride (HF) etch process. Thus, the controllable formation of the cavity for the mechanical movement of NEM memory switches can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any places and metal layers of an M3D CMOS-NEM hybrid chip, which makes circuit design easier and more volume-efficient. The feasibility of our proposed method is verified based on experimental results.

Subject Areas

CMOS-NEMS; NEMS; NEM memory switch; encapsulation; M3D

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