The aim of this study was to investigate the effect of condensed tannin (CTs) with differing molecular weight on their capacity to modify the fatty acid profile in milk. Twenty multiparous crossbred lactating dairy goats were assigned in a randomized complete block design (RCBD), and were subjected to receive the dietary treatments as followings; T1: control (with no CTs supplementation), T2: supplemented with mangosteen peel in a concentrate as a source of low molecular weight CTs at level of 3.0 %DM of CTs equivalent, T3: supplemented with the same diet with T2 but added with polyethylene glycol (PEG, as tannin inactivator) as the control of T2, and T4: supplemented with quebracho CT extract (UNITAN ATO, Buenos Aires, Argentina; 75-77 % tannins) in a concentrate as a source of high molecular weight CTs at level of 3.0 %DM of CTs equivalent, and T5) supplemented with the same diet with T4 but added with PEG as the control of T4. No significant change was detected for feed intake and nutrient digestibility indicate that CTs at level of 3.0 %DM of diet did not showed the detrimental effect to feed intake and nutrient digestibility, however, ruminal fermentation parameters and milk yield and milk compositions did not affected by different source of CT inclusion.

This paper studies the performance improvement of the IEEE 802.15.4 nonbeacon-enabled mode originated by the inclusion of the Request-To-Send/Clear-To-Send (RTS/CTS) handshake mechanism resulting in frame concatenation. Under IEEE 802.15.4 employing RTS/CTS, the backoff procedure is not repeated for each data frame sent but only for each RTS/CTS set. The maximum throughput and minimum delay performance are mathematically derived for both the Chirp Spread Spectrum and Direct Sequence Spread Spectrum Physical layers for the 2.4 GHz band. Results show that the utilization of RTS/CTS significantly enhances the performance of IEEE 802.15.4 applied to healthcare in terms of bandwidth efficiency.

Clock Network Design (CDN) is a critical step while designing any Integrated-Circuits (ICs). It holds vital importance in the performance of entire circuit. Due to continuous scaling, 3D ICs stacked with TSV are gaining importance, with an objective to continue with the Moore's law. Through-Silicon-Via (TSV) provides the vertical interconnection between two die, which allows the electrical signal to flow through it. 3D ICs has many advantages over conventional 2D planar ICs like reduced power, area, cost, wire-length etc. The proposed work is mainly focused on power reduction and obstacle avoidance for 3D ICs. Various techniques have already been introduced for minimizing clock power within specified clock constraints of the 3D CND network. Proposed 3D Clock Tree Synthesis (CTS) is a combination of various algorithms with an objective to meet reduction in power as well as avoidance of obstacle or blockages while routing the clock signal from one sink to other sink. These blockages like RAM, ROM, PLL etc. are fixed during the placement process. The work is carried out mainly in three steps- first is Generation of 3D Clock tree avoiding the blockages, then Buffering and Embedding and finally validating the results by SPICE simulation. The experimental result shows that our CTS approach results in significant 9% reduction in power as compare to the existing work.