From Preserved Microarchitectural State to Recovery-Aware Scheduling in RISC-V Systems

1. Introduction

Fast and predictable recovery from preemption remains an important concern in real-time and embedded processor design. Conventional task switching may disrupt useful execution by requiring architectural state transfer, pipeline flushing, and subsequent pipeline refill before the resumed task can again retire instructions. A broad range of architectural techniques has therefore been proposed to reduce or hide this disruption. Differential multithreading retains thread-specific pipeline state across thread changes [1], while Continuous Flow Multithreading stores multiple microarchitectural states within the pipeline to avoid conventional flushing [2]. Predictability-oriented architectures such as FlexPRET use hardware-threaded execution to control timing interference [3], whereas nMPRA employs independently remapped processor and pipeline resources under hardware scheduling [4]. More recent RISC-V designs accelerate interrupt and context handling through dedicated microarchitectural mechanisms, including CV32RT [5], predictable context-switch support for mixed-criticality systems [6], and joint exploration of processor microarchitecture and real-time operating system (RTOS) support for reducing context-switch latency [7]. These approaches show that retaining, replicating, or rapidly restoring execution state can substantially reduce the disruption caused by preemption.

Preserved microarchitectural state, however, is normally treated as passive execution state: the scheduler first decides which task should run, and the retained state is subsequently used to resume that task efficiently. A different question arises when several runnable contexts are already equivalent under the scheduler's primary eligibility and priority rules. Although such contexts are indistinguishable from the perspective of the primary scheduling policy, their preserved pipeline conditions may differ substantially. One context may contain instructions close to retirement, whereas another may retain unresolved dependencies, a younger load, or a control-flow condition that delays useful progress. Consequently, scheduler-equivalent contexts need not be recovery-equivalent during the first cycles after activation.

This observation motivates the central question addressed in this work: can preserved pre-activation microarchitectural state be transformed into a reliable scheduling signal for discriminating among otherwise equivalent runnable contexts? Answering this question requires more than demonstrating that preserved state contains information. The relevant state must first be shown to rank alternative contexts according to their expected short-horizon execution progress; it must then be represented compactly enough to support practical selection; and finally, the scheduling policy must use that information without overriding the primary scheduler's eligibility and priority semantics.

Our previous work established the execution framework required to investigate this problem. The nSim-RV framework was introduced for reproducible, scheduler-aware timing evaluation under increasing task concurrency [8]. Subsequent studies examined hardware-assisted preserved-context task switching [9], compared conventional and preserved-context switching behavior [10], and evaluated nMPRA- and nHSE-based real-time microarchitectures [11]. These studies characterized switching disruption, preserved-context execution, scheduler interaction, and timing scalability, but they did not use preserved microarchitectural state to discriminate among scheduler-equivalent runnable contexts. The present work therefore addresses a distinct problem: using preserved state not only to resume execution, but also to inform which eligible context should be resumed.

The proposed methodology proceeds in two stages. First, we evaluate the recovery rankability of preserved microarchitectural state using pre-activation pipeline information and actual short-horizon retirement after activation. This analysis shows that coarse pipeline occupancy alone provides limited discrimination and that instruction-class information is particularly important for predicting relative recovery behavior. We therefore evaluate a family of offline compact analysis representations to characterize the rankability–complexity trade-off and separately reconstruct the deployed 16-bit runtime descriptor, denoted C16. The deployed descriptor combines a stage-valid mask, head-instruction class, dependency information, and load-use and redirect indicators into a compact recovery-oriented representation.

Second, we study how such information should be consumed by the scheduler. Four progressively informed policies are evaluated. S0 preserves the original deterministic selection rule and provides the uninformed baseline. S1 introduces a coarse recovery-onset estimate. S2 uses richer C16-based ranking directly. S3, the final policy, combines C16 with a guarded selection rule and bounded residency, allowing recovery information to influence the decision only among candidates already equivalent under the scheduler's primary rules. This policy progression is important because the availability of richer preserved-state information does not itself guarantee better scheduling decisions. Instead, the experiments show that the representation of recovery state and the policy that consumes it must be considered jointly.

The evaluation comprises 40 matched configurations spanning two configuration families, five embedded workloads, 16 and 32 tasks, and four- and five-stage RISC-V pipelines. At the primary four-cycle recovery horizon, S3 improves cumulative retirement relative to S0 in 32 of 40 configurations and achieves the highest R(4) among the four evaluated policies in 29 configurations. The mean configuration-level S3–S0 gain is 0.2574 retired instructions. The observed benefit is consistently larger for the evaluated five-stage pipeline: S3 outperforms S0 in all 20 five-stage configurations, and the five-stage gain exceeds its matched four-stage counterpart in every family–workload–task-count comparison. At the same time, eight losses remain on the four-stage pipeline, showing that the benefit is not universal and motivating an explicit analysis of unfavorable recovery decisions rather than relying only on aggregate improvements.

2. Background and Related Work

Conventional preemptive execution separates task scheduling from processor-state management. The scheduler determines which runnable task should execute according to a task-level ordering policy, whereas the processor and operating system are responsible for preserving the architectural state required for later continuation. Transient microarchitectural state is commonly discarded, reconstructed, or indirectly recovered after a context change. Pipeline flushing and refill, architectural context management, and memory-system interference can therefore delay the return to useful execution following a scheduling decision.

Classical real-time scheduling policies establish execution preference from temporal task parameters rather than from microarchitectural execution state. Rate-Monotonic (RM) assigns fixed priorities according to task periods, whereas Earliest Deadline First (EDF) dynamically orders eligible jobs according to their absolute deadlines [12]. For periodic task systems with constrained deadlines, Deadline-Monotonic (DM) assigns higher fixed priority to tasks with shorter relative deadlines [13]. These policies define primary scheduling relations: they determine eligibility or ordering from timing attributes without considering whether one runnable task retains a more favorable pipeline condition than another. Recovery-aware selection considered in this work does not modify these primary relations. Under EDF, for example, a job with an earlier absolute deadline remains preferred; preserved-state information can affect selection only when the primary scheduling relation does not distinguish the remaining candidates.

Architectural approaches to reducing context-change disruption retain or replicate execution state closer to the processor. Differential multithreading (dMT) preserves thread-specific pipeline state so that a suspended thread can later continue without reconstructing all transient execution state [1]. Continuous Flow Multithreading (CFMT) employs multistate pipeline storage to retain the microarchitectural state of multiple threads and avoid conventional pipeline flushing during thread changes [2]. FlexPRET uses fine-grained hardware multithreading and timing-oriented processor organization to provide predictable execution for mixed-criticality workloads [3]. The nMPRA architecture associates independently remapped processor resources and pipeline registers with multiple execution contexts under hardware scheduling [4]. These mechanisms establish that preserved or replicated execution state can reduce the disturbance associated with changing the active thread or task. They do not, however, use differences among the preserved states of several scheduler-equivalent runnable contexts as an input to the task-selection decision.

Recent RISC-V work has also targeted interrupt and context-switch latency through dedicated architectural support. CV32RT introduces microarchitectural mechanisms for fast interrupt handling and context switching in RISC-V microcontrollers [5]. Nurmi et al. investigate hardware support intended to make context switching efficient and predictable in real-time and mixed-criticality systems [6]. Scheck et al. co-explore RISC-V processor microarchitectures and FreeRTOS extensions and introduce hardware support that reduces context-switch latency and jitter [7]. In each case, the architectural contribution accelerates or regularizes the transition associated with a scheduling decision; the preserved or accelerated state is not used to rank multiple candidates that are already equivalent under the primary scheduler.

Context-switch disruption has also been addressed without preserving a complete in-flight pipeline state. PRET-oriented architectures use hardware multithreading to obtain composable timing behavior and reduce timing interference between concurrent programs [14]. Zhou and Petrov employ embedded-processor customization to reduce context-switch overhead in real-time and control applications [15]. Mische et al. use simultaneous multithreading to hide context-switch times for larger real-time task sets [16]. Yamazawa et al. retain contexts close to a multicore RISC-V processor through a context-cache mechanism [17]. Selective Pipeline Flush preserves unaffected in-flight instructions instead of indiscriminately removing pipeline contents when recovery from a control or execution event is required [18]. Nurmi et al. investigate dedicated hardware mechanisms for eliminating context-switch latency in processor-based hard real-time systems [19]. These techniques reduce the cost of preserving, restoring, or re-establishing execution state once a task or thread change has been determined; they do not use the retained state to determine which scheduler-equivalent task should be selected.

Cache-related preemption research addresses a different microarchitectural consequence of task switching. Altmeyer and Maiza survey methods for bounding cache-related preemption delay (CRPD) and refine the useful-cache-block abstraction used to estimate additional cache misses caused by preemption [20]. Their analysis characterizes the execution-time penalty caused when useful cache contents of a preempted task are displaced before the task resumes. Bril et al. incorporate CRPD into response-time analysis for fixed-priority preemption-threshold scheduling and develop a threshold-assignment procedure that explicitly accounts for cache-related preemption costs [21]. Buttazzo et al. survey limited-preemptive scheduling models in which preemption is restricted to selected intervals, points, or scheduling conditions in order to balance responsiveness, predictability, and preemption overhead [22]. These approaches make microarchitectural preemption cost relevant to schedulability analysis or to the conditions under which preemption is permitted. Recovery-aware scheduling addresses another decision: it does not estimate the cost of a potential preemption or prevent a higher-priority preemption, but selects between contexts that the primary scheduler already considers equivalent. The bounded residency employed by the S3 policy is correspondingly different from a non-preemptive region or a preemption threshold because it is immediately revoked when the selected context no longer satisfies the primary scheduler's eligibility relation.

Processor-cache affinity provides a closer precedent for using residual microarchitectural state as a scheduling signal. Squillante and Lazowska observe that a task can benefit from being redispatched to a processor on which useful data from its previous execution may remain cached, and they formulate scheduling policies that explicitly account for processor-cache affinity [23]. Torrellas et al. experimentally evaluate cache-affinity scheduling and show that preferentially returning a process to a processor on which it recently executed can reduce cache misses and execution time [24]. Cache-affinity scheduling therefore demonstrates that residual processor state can legitimately influence a dispatch decision. The information source and decision problem nevertheless differ from those considered here: cache affinity concerns the association between a task and a processor's residual cache contents, whereas recovery-aware selection compares the preserved in-flight pipeline states belonging to several runnable execution contexts without changing their processor placement.

Cache-aware scheduling has subsequently incorporated cache requirements, locality, and contention into real-time and multicore decisions. Guan et al. formulate scheduling and schedulability analysis for multicore real-time systems in which tasks have both timing requirements and cache-space constraints; their approach isolates shared-cache partitions and derives schedulability tests for the resulting resource-constrained task model [25]. Akturk and Ozturk use runtime cache-access characteristics and adaptive scheduling decisions to reduce inter-thread contention in chip multiprocessors [26]. Tessler et al. exploit instruction-cache sharing between related execution requests in cache-aware federated scheduling and use this information to improve schedulability and reduce processor requirements [27]. Zhao et al. propose a dynamic multicore allocation approach that learns cache recency from execution history and uses the resulting estimates when allocating parallel jobs to cores [28].

The interaction between established real-time scheduling policies and dynamic cache allocation has also been studied directly. Lin et al. consider preemptive global EDF in systems with dynamically allocated cache partitions and derive LAG-based and utilization-based schedulability conditions that account for both processor and cache availability [29]. Yi et al. address cache-aware directed acyclic graph (DAG) scheduling using an affinity-aware node-priority mechanism and deferred execution to exploit cache locality while reducing contention and DAG makespan [30]. These works show that cache state or cache-resource availability can participate directly in task ordering, allocation, or schedulability analysis. Their optimization variables concern cache partitions, core allocation, node ordering, or processor affinity rather than useful instructions already resident in a preserved execution pipeline.

Microarchitectural information has also been used at the hardware-thread and instruction-issue level. Eni et al. use instruction-type information available in a hardware-multithreaded RISC-V pipeline to guide event-based issue scheduling and improve pipeline utilization relative to conventional Round-Robin and coarse-grain issue policies [31]. Cache-Conscious Wavefront Scheduling uses cache feedback to influence wavefront issue decisions and reduce destructive cache interference [32]. Ribo and Greenberg propose prefetch- and issue-scheduling mechanisms for a superscalar multithreaded RISC-V processor; their scheduler selects among hardware threads to improve processor utilization and instructions per cycle (IPC) [33]. These mechanisms use microarchitectural observations as scheduling inputs, but their decisions are made at the instruction-issue or hardware-thread scheduling level. Recovery-aware selection is invoked at a task/context activation boundary and only after the primary scheduler has already established which runnable contexts are equivalent in eligibility and priority. Table 1 summarizes these distinctions by comparing the information source, its role in scheduling, the decision level at which it is applied, and the main distinction from the recovery-aware selection considered in this work.

Table 1 shows that the closest precedents use microarchitectural information at different decision levels or for different objectives. In contrast, the proposed mechanism uses preserved in-flight pipeline state only as a secondary preference at task/context activation, after the primary scheduler has established equivalence.

Previous studies by the authors established the simulation and preserved-context execution basis used in this work [8,9,10,11]. The present study builds on that infrastructure but addresses a different question: whether preserved pre-activation microarchitectural state can discriminate among scheduler-equivalent runnable contexts and thereby support a secondary context-selection decision.

To the best of our knowledge, the prior work identified above does not jointly address three properties considered in this study: (i) preserved in-flight pipeline state is used as the selection signal; (ii) the signal is permitted to influence selection only within an equivalence class already established by the primary scheduler; and (iii) candidate preference is defined against an explicit post-activation recovery objective based on short-horizon instruction retirement. This formulation keeps recovery preference subordinate to the primary scheduling policy and separates the proposed mechanism from context-switch acceleration, preemption-cost analysis, cache-aware allocation, processor affinity, and instruction-issue scheduling.

The availability of preserved state alone does not establish that it is suitable for this purpose. A state representation may contain insufficient information to distinguish contexts with different recovery behavior, while exposing complete pipeline state may impose unnecessary implementation complexity. An informative representation can also produce unfavorable scheduling decisions when used without an appropriate decision rule. The analysis that follows therefore first defines the post-activation recovery objective, then evaluates the rankability of preserved pre-activation state, derives a compact recovery descriptor, and finally examines how progressively more informed S0–S3 policies use that descriptor without changing the authority of the primary scheduler.

3. Problem Formulation and Recovery Metric

Consider a preserved-context processor in which the primary scheduler first determines the set E_t of runnable contexts that are eligible for execution at scheduling instant t according to its task-class, priority, or policy-specific rules. Let ≺_P denote the strict preference relation induced by the primary scheduling policy P before its deterministic fallback rule is applied. Two eligible contexts i,j ∈ E_t are considered scheduler-equivalent, denoted i∼_Pj, when neither i≺_Pj nor j≺_Pi. Recovery-aware selection is considered only within such an equivalence class. It therefore does not alter eligibility, promote a lower-priority context, or replace the underlying scheduling policy. For any eligible context i, define its primary-scheduler equivalence class at scheduling instant t as:

$ℰ$_P(i|t) = {j ∈ E_t:j∼_Pi}

(1)

When the relevant equivalence class is unambiguous, it is denoted simply by $ℰ$_P(t). Let x_j denote the complete preserved pre-activation microarchitectural state of candidate j. If future recovery were observable at the scheduling instant, the corresponding oracle decision for horizon H, would be:

$$j_{\mathrm{oracle}}^{*}\left(t\right|H)=\arg \underset{j\in {\mathcal{E}}_P\left(t\right)}{\max }{R}_j\left(H\right)$$

(2)

This oracle is not implementable online because R_j(H) is known only after activation. The practical problem is therefore to construct a causal ranking function g(x_j), evaluated exclusively from pre-activation state, such that:

$$\widehat{j}\left(t\right)=\arg \underset{j\in {\mathcal{E}}_P\left(t\right)}{\max }g\left(x_j\right)$$

(3)

approximates the oracle ordering while preserving the equivalence constraints imposed by the primary scheduler.

This distinction is central to the formulation adopted here. Two scheduler-equivalent contexts may preserve different microarchitectural states at the instant at which a selection decision is made. One context may contain valid instructions close to retirement, whereas another may resume with unresolved dependencies, a load-related hazard, or a control-flow condition that delays immediate progress. The relevant question is consequently not whether a context is runnable, but whether its preserved pre-activation state contains information about the amount of useful execution that can be recovered immediately after activation.

Let t_act denote the cycle at which context i becomes architecturally active. For a short observation horizon H, the activation-level recovery of context i is defined as:

$$R_{i\left(H\right)}=\sum _{c=t_{\mathit{act}}}^{t_{\mathit{act}}+H-1}{I}_{i\left(c\right)}$$

(4)

where I_i(c) = 1 if context i retires an instruction in cycle c, and I_i(c) = 0 otherwise.

Thus, Ri(H) counts the number of instructions retired by the activated context during the first H cycles of execution following activation. The observation window begins at architectural activation rather than at the preceding scheduler decision. Scheduler execution time and explicit activation latency are therefore excluded from the recovery measurement, allowing the metric to isolate the short-horizon execution behavior of the selected preserved context itself.

The experiments consider H ∈ {1, 2, 4}. The corresponding Ri(1), Ri(2), and Ri(4) values expose progressively longer portions of the immediate post-activation behavior. Ri(1) captures only the first retirement opportunity, whereas Ri(4) allows short dependency chains, pipeline occupancy, and near-term execution conditions to influence the observation. The four-cycle horizon is used as the primary recovery metric throughout the subsequent ranking and scheduling analysis because it remains local to the activation event while providing a more informative indication of near-term progress than a single-cycle observation.

For a policy p and a matched configuration k, $𝒱$_(p,k)(H) denotes the set of activation events for which the complete H-cycle observation window is valid. The configuration-level mean recovery is defined as:

$${\bar{R}}_{\left(p,k\right)\left(H\right)}={\displaystyle \frac{1}{\left|{\mathcal{V}}_{\left(p,k\right)\left(H\right)}\right|}}\sum _{i\in {\mathcal{V}}_{\left(p,k\right)\left(H\right)}}{R}_{i\left(H\right)}$$

(5)

The primary configuration-level comparison between S3 and S0 is then defined as:

$$\Delta R_{k\left(4\right)}={\bar{R}}_{\left(S3,k\right)\left(4\right)}-{\bar{R}}_{\left(S0,k\right)\left(4\right)}$$

(6)

Accordingly, ΔR_k(4) is a configuration-level difference between two means rather than an individual activation-level recovery count. Positive values indicate higher mean four-cycle recovery under S3, whereas negative values indicate higher mean recovery under S0. Because configuration-level values aggregate multiple activation events, they may be fractional even though each individual R_i(H) measurement is an integer count.

An observation is considered valid only when the complete requested recovery window is available. If the selected context is re-preempted or otherwise loses execution before the H-cycle interval is completed, the corresponding Ri(H) value is treated as censored rather than assigned a value of zero. This avoids conflating incomplete observation with genuine absence of retirement progress.

The recovery metric is intentionally local. It does not represent application throughput, execution time, worst-case execution time, response time, deadline satisfaction, or scheduler fairness. Instead, it answers a narrower question that is directly aligned with the proposed use of preserved state: given multiple contexts that are already equivalent under the primary scheduling policy, does selecting one preserved microarchitectural state rather than another lead to more useful instruction retirement immediately after activation?

This formulation separates the scheduling problem into two subsequent questions. First, it must be established whether the preserved pre-activation state contains enough information to rank scheduler-equivalent contexts according to their future R(4) behavior. Second, if such information exists, it must be represented and consumed in a form that improves selection without disturbing the authority of the primary scheduler. The first question is addressed in the following section through a recovery-rankability analysis of the preserved pipeline state.

4. Recovery Rankability of Preserved State

Before using preserved microarchitectural state as a scheduling signal, it is necessary to establish whether the state observed before activation contains sufficient information to discriminate between contexts according to their subsequent recovery behavior. We refer to this property as recovery rankability. Let $𝒫$ denote the set of evaluated candidate pairs (a|b) for which the observed four-cycle recoveries are unequal; pairs with tied R(4) targets are excluded from directional ranking evaluation. For each candidate pair (a,b) ∈ $𝒫$, define the observed recovery ordering as:

y_ab = sgn (R_a(4) − R_b(4))

(7)

Let ${\widehat{y}}_{\mathit{ab}}$ denote the ordering predicted from the evaluated pre-activation state representation. The pairwise ranking accuracy is then:

$$A={\displaystyle \frac{1}{\mid \mathcal{P}\mid }}\sum _{\left(a\right|b)\in \mathcal{P}}1\hspace{0.17em}\left({\widehat{y}}_{\mathit{ab}}=y_{\mathit{ab}}\right)$$

(8)

Recovery rankability therefore quantifies how frequently information available before activation reproduces the ordering that is subsequently observed in short-horizon recovery.

The analysis was performed on a dedicated discovery dataset comprising 253,250 activation events with valid R(4) observations. The dataset covers five workloads—CoreMark [34], CRC32, Dhrystone [35], MatMult-Int, and StateMate—under both four-stage and five-stage preserved-context pipeline configurations. CRC32, MatMult-Int, and StateMate were derived from the corresponding embedded-benchmark implementations included in the evaluated benchmark suite [36]. All candidate features were sampled from the incoming context before execution resumed. Consequently, no post-activation retirement, stall, branch, memory, or other future execution information was available to the ranking process.

As an initial reference, a coarse recovery predictor based on limited preserved-state information achieved a pooled pairwise ranking accuracy of 73.89% and an unweighted macro accuracy of 76.39%. This result already indicates that scheduler-equivalent contexts are not microarchitecturally interchangeable: information available before activation is statistically informative about their relative short-horizon recovery. However, it also leaves a substantial fraction of candidate pairs incorrectly ordered, motivating an examination of which parts of the preserved state carry the relevant information.

A richer state representation was therefore evaluated using the validity and instruction information associated with the preserved pipeline stages together with dependency and control indicators. The full-state reference was evaluated offline using a random-forest model over the complete observable pre-activation feature set. Its purpose was to estimate the recovery-ranking information available in the preserved state rather than to define a deployable scheduling mechanism. Evaluation followed a leave-one-workload-out protocol: for each reported workload result, the model was trained on the remaining workloads and evaluated only on events from the held-out workload. Under this workload-separated evaluation, the full-state model achieved a pooled pairwise ranking accuracy of 93.36% and an unweighted macro accuracy of 93.34%. Per-workload accuracies were 100.00% for CoreMark, 97.66% for CRC32, 100.00% for Dhrystone, 74.63% for MatMult-Int, and 94.40% for StateMate. The substantially lower value for MatMult-Int also shows that recovery rankability is workload dependent and that preserved state does not provide an equally strong ordering signal for every instruction stream.

Feature ablation showed that instruction-class information contributed most strongly to recovery rankability, followed by pipeline-stage validity, read-after-write (RAW) dependency count, control and hazard information, and load/store indicators. The corresponding decreases in pooled pairwise ranking accuracy are summarized in Table 2.

The ablation results show that pipeline occupancy alone is insufficient to characterize recovery potential. Instruction-class information provides the strongest discriminative contribution, while stage validity, dependency structure, and control or hazard conditions provide complementary information. These results argue against recovery representations based solely on occupancy masks or preserved-instruction counts.

Ranking quality was additionally characterized through selection regret. For an evaluated candidate pair e, let $j_e^{*}$ denote the oracle candidate with the larger observed R(4), and let ${\widehat{j}}_e$ denote the candidate selected by the evaluated ranking representation. The event-level regret is

$${\rho }_e=R_{j_e^{*}}\left(4\right)-R_{{\widehat{j}}_e}\left(4\right)$$

(9)

and the mean regret over N evaluated selections is

$$\overline{\rho }={\displaystyle \frac{1}{N}}{\displaystyle \sum _{e=1}^N}{\rho }_e$$

(10)

A value of zero corresponds to oracle-equivalent selection, whereas larger values quantify the short-horizon retirement opportunity lost because of an incorrect ranking decision.

The usefulness of a ranking representation was also evaluated in terms of the recovery obtained when it is used to select between candidates. An oracle that always selects the candidate with the higher observed R(4) achieves an expected recovery of 3.1556 retired instructions over the four-cycle horizon. The coarse reference reaches 2.8066, corresponding to a mean regret of 0.3490. The deployed C16 runtime representation reaches 2.9331 and reduces mean regret to 0.2226. For comparison, the full-state model reaches 3.0800, with a mean regret of 0.0756.

These results establish two properties required by recovery-aware scheduling. First, the preserved pre-activation pipeline state contains substantial information about subsequent short-horizon retirement behavior. Second, the useful information is not uniformly distributed across the state representation: instruction class, pipeline validity, dependencies, and selected hazard conditions contribute differently to recovery discrimination. The problem is therefore not simply to expose more state to the scheduler, but to identify a compact representation that retains enough of this ranking capability to support practical selection.

The next section addresses this representation problem by distinguishing the offline compact analysis representations from the deployed runtime C16 descriptor.

5. Compact Recovery Descriptor Design

The rankability analysis shows that preserved microarchitectural state contains useful information about subsequent recovery, but exposing the complete preserved pipeline state directly to the scheduler would be unnecessarily complex. The representation used for recovery-aware selection should therefore preserve the most informative state components while remaining compact enough to support low-overhead comparison among scheduler-equivalent candidates.

To explore this trade-off, several compact state representations were evaluated against the full preserved-state model. The candidate representations progressively incorporate pipeline occupancy, dependency, instruction-class, memory-operation, and control information. Their pairwise recovery-ranking accuracies are summarized in Table 3.

The results show that representation size alone does not determine ranking quality. Among the offline compact analysis representations, C16_offline achieves 82.72% pooled and 82.40% unweighted macro accuracy, while C20 reaches 85.64% and 85.43%, respectively, and C24 reaches 85.32% and 85.75%. The independently reconstructed deployed C16_runtime achieves 84.63% pooled and 86.81% unweighted macro accuracy. The full-state reference remains the most accurate, at 93.36% pooled and 93.34% macro accuracy.

The offline sweep was used to characterize the rankability–complexity trade-off, but C16_offline is not identical to the deployed runtime word. The scheduling policies evaluated in this work use C16_runtime, whose 16-bit representation was verified directly against the frozen implementation. The 16-bit design point is therefore treated as a compact operating point rather than as a claim of global optimality.

The deployed C16 runtime descriptor uses a 16-bit storage container. Bits 0–4 encode the stage-valid mask, bits 5–7 encode the head-instruction class, bits 8–9 encode the RAW-dependency count, bit 10 encodes the load-use indicator, and bit 11 encodes the pending-redirect indicator. Bits 12 and 13 are fixed to zero in the frozen implementation, while bits 14–15 are reserved and remain zero. Formally, let $𝒳$ denote the space of observable preserved pre-activation microarchitectural states. C16 defines a deterministic compression mapping

f₁₆:$𝒳$ → {0|1}¹⁶, C16 = f₁₆(x)

(11)

The 16-bit output is treated as a logical descriptor rather than as a reconstructed pipeline state; bits 0–11 carry runtime state in the frozen implementation, while bits 12–15 remain zero. The mapping is intentionally lossy: distinct preserved states may produce the same descriptor. The descriptor-design problem is therefore not exact state reconstruction, but retention of sufficient ordering information for recovery-aware selection under a fixed representation budget. The logical organization and bit allocation of the C16 descriptor are shown in Figure 1.

The descriptor is not intended to reproduce the full preserved pipeline state. Instead, it retains the feature groups shown by the rankability analysis to carry the strongest discriminative information while discarding state that provided lower incremental benefit for short-horizon recovery ordering.

A scalar recovery score is computed from C16 as:

S(C16) = H_CLUT + 1(raw_dep > 0)

(12)

Here HC_LUT is the fixed lookup contribution associated with the three-bit head-instruction class, and 1(⋅) is the indicator function, equal to one when its argument is true and zero otherwise. The H_CLUTH values are 0, 0, 2, 2, 3, 3, 0, and 0 for head-class codes 000–111, respectively. The deployed encoder emits codes 000–100, corresponding to other/none, load, store, branch, and jump; codes 101–111 are reserved. The variable raw_dep is the two-bit RAW-dependency count encoded in bits 8–9 of C16. The load-use and redirect indicators, encoded in bits 10 and 11, remain part of C16 but do not contribute directly to the S3 score. The resulting score is evaluated only among contexts already identified as equivalent by the primary scheduler.

Importantly, C16 and the recovery-aware scheduling policy are separate mechanisms. C16 is only a representation of preserved microarchitectural state, and S(C16) is only a ranking signal. Whether and how that signal is allowed to influence context selection is determined by the scheduling policy. This distinction is essential because the rankability analysis shows that even informative state representations are imperfect: the deployed C16 runtime representation achieves 84.63% pooled and 86.81% unweighted macro pairwise ranking accuracy rather than perfect ordering. A policy that trusts the descriptor unconditionally can therefore still make harmful selections.

6. Recovery-Aware Scheduling Policies

The preserved-state descriptor introduced in the previous section provides a recovery-oriented ranking signal, but it does not by itself define how that signal should influence scheduling. To separate the effect of state representation from the effect of the decision rule, four progressively informed policies, denoted S0–S3, were evaluated under the same primary scheduling constraints.

S0 is the deterministic baseline. The primary scheduler first determines the set of eligible runnable contexts and applies its normal task-class and priority rules. When multiple candidates remain equivalent, S0 selects among them using the existing deterministic fallback rule. No preserved microarchitectural information is used in this decision.

S1 introduces onset-informed selection. It uses a coarse estimate of recovery onset derived exclusively from the preserved pre-activation pipeline state and therefore represents the simplest recovery-aware alternative to S0. The corresponding onset estimate is computed as

$$L_R^{\mathit{pred}}=s{5}_{\mathit{valid}}+2s{4}_{\mathit{valid}}+\mathit{loa}{d}_{\mathit{us}{e}_{\mathit{hazard}}}$$

(13)

where s5_valid and s4_valid correspond to the write-back (WB) and memory (MEM) validity terms used by the locked S1 implementation, and $\mathit{loa}{d}_{\mathit{us}{e}_{\mathit{hazard}}}$ is the preserved load-use indicator. In the five-stage organization all three terms can contribute. In the four-stage organization, the memory (MEM) and write-back (WB) fields used by S1 remain inactive, so the S1 score reduces to the load-use indicator. The largest score is preferred, with the lower task identifier resolving a tie.

The policy primarily reflects expected first-retirement behavior and does not use the richer instruction-class and dependency representation encoded by C16. S1 is included to determine whether coarse information about how rapidly a context is expected to resume useful retirement is sufficient to improve selection.

S2 uses the deployed C16 runtime word through a distinct direct heuristic. Let M_stage denote the numerical value of the five-bit stage-valid mask (bits 0–4), and let b₁₀ and b₁₁ denote the load-use and redirect bits. S2 evaluates S_S2(C16) = M_stage − 2b₁₀ − 3b₁₁, prefers the largest score, and resolves ties by the lower task identifier. S2 therefore tests direct heuristic use of the runtime descriptor without the guarded score and bounded-residency mechanism introduced by S3.

The final policy, S3, retains C16 ranking but constrains its influence through a guarded decision rule. The primary scheduler remains responsible for eligibility and priority ordering. Recovery-aware selection is activated only after the scheduler has identified two or more candidates that are equivalent under those primary rules. Let j₀ denote the candidate that would be selected by the S0 fallback rule and j_r the candidate with the highest C16 recovery score. S3 replaces the S0 candidate only when:

$$S\left(C{16}_{j_r}\right)-S\left(C{16}_{j_0}\right)\ge 1$$

(14)

Equivalently, letting π_S0(E_t) = j₀, the S3 selection rule can be written as:

$${\pi }_{S3}\left(E_t\right)=j_r\mathrm{if}{j}_r\ne j_0\wedge \mathit{S}\left(C{16}_{j_r}\right)-S\left(C{16}_{j_0}\right)\ge 1$$

(15)

π_S3(E_t) = j₀ otherwise

Equation (15) makes explicit that the recovery-aware rule is evaluated only after the primary scheduler has restricted the candidate set to a scheduler-equivalent class.

Otherwise, the deterministic S0 choice is preserved. The configured guard therefore requires the recovery-preferred candidate to exceed the S0 fallback by at least one score unit before preserved-state information is allowed to change the selection. When this condition is satisfied, the selected recovery-aware context is retained for a four-cycle residency interval while it remains eligible under the primary scheduler. Loss of eligibility terminates the residency immediately and restores full authority to the primary scheduling rules. The residency interval is part of the locked C16_V2 policy used throughout the final evaluation and spans the same short horizon used by the primary R(4) recovery metric. The complete decision path of the guarded S3 policy is shown in Figure 2.

Proposition 1 (Primary-order preservation). Recovery-aware selection cannot reverse a strict ordering imposed by the primary scheduler.

Proof. Recovery scores are evaluated only among contexts belonging to the same primary-scheduler equivalence class. If two eligible contexts i and j are strictly ordered by the primary policy, then i̸∼_Pj; consequently, they cannot be compared through the recovery-aware rule. Therefore, C16-based selection cannot replace a primary scheduling preference with a recovery preference.

Corollary 1 (Fallback consistency). If the recovery candidate does not exceed the S0 candidate by at least one score unit, then π_S3(E_t) = π_S0(E_t).

The guarded structure separates scheduler authority from recovery preference. Recovery information never promotes an ineligible context, changes task class, or overrides a stronger priority ordering. It is consulted only within the equivalence class already exposed by the primary scheduler. S3 should therefore be interpreted as a secondary tie-breaking mechanism rather than as a replacement for conventional policies such as fixed-priority, Round-Robin, or Earliest Deadline First scheduling. Under a deadline-driven scheduler, for example, a context with an earlier deadline remains preferred; C16 can influence the decision only when the primary policy considers the competing candidates equivalent.

The progression from S0 to S3 also provides a controlled way to distinguish the usefulness of the state descriptor from the usefulness of the policy that consumes it. If richer microarchitectural information were sufficient by itself, S2 would be expected to consistently outperform the baseline. The final experiments show that this is not the case: direct use of the richer recovery ranking can still produce harmful decisions. S3 therefore combines the informative C16 representation with conservative decision logic intended to suppress weakly supported overrides and stabilize the immediate post-activation interval.

Preserved microarchitectural state becomes useful for scheduling not merely because it is observable, but because it is represented at an appropriate level of abstraction and consumed under constraints that preserve the semantics of the primary scheduler.

7. Experimental Methodology

The experimental methodology was organized into two complementary stages. The first stage was used to characterize the recovery information contained in preserved microarchitectural state and to derive the compact C16 representation. The second stage evaluated how that representation behaves when embedded into the S0–S3 scheduling policies under matched execution conditions. Keeping these stages separate avoids using the final policy-comparison results to define the descriptor evaluated by those same policies.

The discovery and rankability stage generated the dataset described in Section 4 from 10 preserved-context configurations spanning five workloads, two pipeline organizations, and 16 execution contexts. The recorded pre-activation information included stage-valid indicators, instruction-class or opcode information, dependency relationships, load/store properties, load-use conditions, and redirect state. Recovery labels R(1), R(2), and R(4) were obtained from the subsequent execution window and were used only as outcomes, not as predictor inputs.

The discovery dataset was used for three purposes: to establish whether preserved state is recovery-rankable, to quantify the contribution of individual feature groups, and to compare candidate compact representations. Workload-separated evaluation was used for the richer ranking analysis so that recovery predictions for a workload were derived without training on events from that same workload. The resulting analysis produced the feature-ablation results reported in Section 4 and the compact descriptor comparison reported in Section 5.

For the rankability analysis, candidate pairs were formed within each (config_name,L_R) group after lexicographic event-identifier sorting. Each event was compared with at most the next 50 records; equal-R(4) ties were excluded, and at most 1,500 pairs were retained per group. Pair orientation alternated by pair-index parity. Leave-one-workload-out evaluation trained on the other four workloads. Pooled accuracy is the fraction of correct predictions across all held-out pairs, whereas macro accuracy is the unweighted mean of the five workload-specific accuracies.

The policy-evaluation stage was performed using a separate matched campaign covering two experimental families, denoted A and B. The two families differ in the structure of scheduler equivalence. In Family A, all tasks belong to the same priority level, creating a broad equivalence class in which recovery-aware tie breaking can operate among many otherwise equal candidates. Family B partitions the task set into priority groups of four tasks each. Consequently, the N16 (16-task) configurations contain four priority levels and the N32 (32-task) configurations contain eight, while recovery-aware selection remains restricted to candidates within the same priority group. The two families therefore evaluate the policy under different sizes and structures of scheduler-equivalent candidate sets without allowing recovery information to cross priority boundaries. Within each family, the same five workloads were evaluated at 16 and 32 task/context configurations and with four-stage and five-stage pipelines. The resulting matrix contains 40 matched family–workload–task-count–pipeline configurations:

2 families × 5 workloads × 2 task counts × 2 pipeline depths = 40

For each of these 40 configurations, policies S0, S1, S2, and S3 were evaluated under the same workload and simulator configuration. Comparisons between policies were therefore performed only between matched runs that differed in the recovery-selection policy being applied. The complete policy-evaluation matrix is summarized in Table 4. Thus, the evaluation contains 40 matched base configurations. Each base configuration was executed under all four policies S0–S3, yielding 160 policy-specific runs while preserving a 40-unit matched design for statistical comparison.

The four-stage and five-stage pipeline organizations were evaluated separately because pipeline depth changes the amount and organization of preserved in-flight execution state available at a selection point. The comparison is therefore not used to claim a general relationship between pipeline depth and recovery benefit, but to determine whether the observed policy behavior changes consistently across the two evaluated microarchitectural organizations.

The final comparison uses R(4) as the primary activation-level recovery metric defined in Section 3. For each matched configuration k, valid activation events are aggregated as ${\bar{R}}_{\left(p,k\right)\left(4\right)}$, and the main S3 comparison is reported as ΔR_k(4) relative to S0. Configuration-level averages are computed over valid activation events only. The matched configuration, rather than the individual recovery event, is the observational unit used for policy-level comparisons. Recovery events are aggregated within each configuration and are not treated as statistically independent replicates. Events for which the complete requested recovery window is not available are censored according to the validity rule defined earlier and are not converted into zero-recovery observations.

Statistical inference was restricted to the designated primary horizon R(4); the R(1) and R(2) results are retained as descriptive horizon analyses. This avoids treating the three recovery horizons as independent confirmatory tests. Inference was performed on the 40 matched configuration-level differences ΔR_k(4), rather than on individual recovery events. Uncertainty in the mean configuration-level effect was quantified using a bias-corrected and accelerated (BCa) bootstrap confidence interval with 100,000 configuration-level resamples and a fixed PCG64 seed of 20260908. A two-sided exact Wilcoxon signed-rank test with Wilcox zero handling and no continuity correction was used to evaluate the paired S3–S0 differences, with rank-biserial correlation reported as a nonparametric effect-size measure. An exact two-sided binomial sign test was additionally used to evaluate whether the probability of a positive configuration-level difference differs from 0.5, together with an exact 95% confidence interval for the proportion of positive differences.

Policies S1 and S2 are retained as intermediate ablations rather than alternative final proposals. S1 tests whether a coarse recovery signal is sufficient, while S2 tests whether the richer C16 representation can be used directly without the guard and bounded-residency mechanism introduced by S3. Their role is therefore to separate the contribution of additional state information from the contribution of the decision logic that consumes that information.

The final policy-evaluation campaign was executed from the frozen simulator source using a single clean Release build. Policies S0–S3 were selected at runtime from the same executable. Sixteen pre-campaign canary runs covering all four policies and both pipeline/task-count combinations passed the validity checks, after which all 160 policy-specific runs completed successfully. Consequently, all policy comparisons reported in this work use a single simulator executable and are recomputed exclusively from the event files generated by this unified campaign; historical artifacts are retained only for provenance and comparison.

Reproducibility is supported by a frozen artifact package containing the Windows x64 release executable, workload and configuration artifacts, raw discovery and policy outputs, analysis scripts, statistical procedures, checksum manifests, and manuscript numeric source data. The package supports verification and re-analysis of the archived evidence, recomputation of policy metrics from the 160 unified-binary runs, rerunning the documented campaign with the provided executable, reevaluation of the deployed C16 descriptor from the packaged evidence, and regeneration of the source data for Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7 and Figure 3, Figure 4, Figure 5 and Figure 6.

8. Experimental Results

Across the 40 matched configurations, the guarded S3 policy improves four-cycle cumulative retirement relative to S0 in 32 cases (80%), with eight negative differences and no ties. The mean configuration-level gain is 0.2574 retired instructions, with a median of 0.1485. The corresponding mean improvements at the shorter horizons are 0.0801 instructions at R(1) and 0.1561 at R(2). At R(2), S3 is positive in 34 of the 40 configurations, while the one- and four-cycle horizons each contain 32 positive cases. These results indicate that the recovery advantage is already observable immediately after activation and remains positive on average as the observation window expands. Table 5 reports the configuration-level S3–S0 recovery differences for the three evaluated recovery horizons.

At the primary R(4) horizon, the mean configuration-level S3–S0 difference of 0.2574 retired instructions has a 95% BCa bootstrap confidence interval of [0.1719, 0.3782]. The paired differences are significantly shifted above zero under a two-sided exact Wilcoxon signed-rank test (W = 69, p = 4.77 × 10⁻⁷), with a rank-biserial correlation of r_rb = 0.832, indicating a strong directional effect across the matched configurations. The complementary exact sign test also rejects equal probability of positive and negative configuration-level differences (32/40 positive; p = 1.82 × 10⁻⁴); the exact 95% confidence interval for the probability of a positive difference is [0.644, 0.909]. These inferential results support a positive configuration-level effect of S3 within the evaluated design space while remaining consistent with the eight negative counterexamples analyzed in Section 9.

The increase in mean recovery from R(1) to R(4) should not be interpreted as a cumulative performance gain over longer execution intervals. The metric remains deliberately local to the activation event. Rather, the horizon analysis shows that the choice made at activation can influence several immediately following retirement opportunities, which motivates the use of R(4) as the primary comparison quantity.

The intermediate policies provide an important contrast. At R(4), S3 exceeds S1 by a mean of 0.3796 instructions and S2 by 0.4083 instructions. More importantly, the richer recovery information used by S1 and S2 does not by itself guarantee improvement over the deterministic S0 baseline. S1 falls below S0 in 19 of the 40 matched configurations, while S2 falls below S0 in 28. By contrast, S3 is below S0 in only eight configurations. This progression supports the distinction introduced earlier between an informative state representation and a policy that consumes that representation conservatively. Figure 3 summarizes the policy progression relative to the S0 baseline by combining the number of configurations with positive and negative four-cycle recovery differences with the corresponding mean ΔR(4).

S1 produces lower recovery than S0 in 19 of 40 configurations, while S2 does so in 28 configurations. In contrast, S3 is below S0 in only eight cases and achieves a positive mean ΔR(4) of 0.2574 retired instructions. These results indicate that increasing the amount of preserved-state information does not by itself ensure improved selection; the decision rule used to consume that information is equally important.

Considering all four policies jointly, S3 achieves the highest R(4) outright in 29 of the 40 configurations, ranks second in three, third in four, and last in four. The result is therefore not driven solely by comparison with a weak baseline; S3 is the best-performing policy in the majority of the matched design points.

The configuration-level S3–S0 differences are shown in Figure 4. Reporting all 40 matched configurations is important because the global mean does not capture the heterogeneous behavior of the policy. The largest positive differences occur in CRC32 configurations, while the strongest negative case is A/MatMult-Int/N16/P4, with ΔR(4) = −0.1173. The coexistence of substantial gains and a smaller set of losses motivates the explicit counterexample analysis in Section 9.

The policy effect varies substantially by workload. CRC32 exhibits the largest mean improvement, 0.7832 retired instructions, followed by CoreMark at 0.1828, StateMate at 0.1246, Dhrystone at 0.1028, and MatMult-Int at 0.0936. These workload-level means indicate that the usefulness of the recovery signal depends on the instruction stream and preserved pipeline condition rather than being uniform across applications. Table 6 summarizes the mean S3–S0 four-cycle recovery gain for each workload.

A particularly clear distinction appears between the evaluated pipeline organizations. The mean ΔR(4) is 0.1235 for the four-stage pipeline and 0.3913 for the five-stage pipeline. The four-stage subset contains 12 positive and eight negative configurations, whereas all 20 five-stage configurations are positive. Moreover, when each family–workload–task-count configuration is paired across pipeline depth, the five-stage gain is larger than its four-stage counterpart in all 20 matched pairs. Figure 5 compares the mean S3–S0 recovery gain by workload for the four-stage and five-stage pipeline organizations.

For all five workloads, the mean ΔR(4) is larger for P5 than for P4. The contrast is particularly pronounced for Dhrystone and MatMult-Int, whose mean P4 values are slightly negative but become clearly positive under P5. CRC32 exhibits the largest gain under both pipeline organizations. Although Figure 5 reports workload-level means, the same directional pattern is present in the complete matched dataset: P5 produces a larger ΔR(4) than P4 in all 20 family–workload–task-count pairs.

This result establishes a strong association within the evaluated design space, but it does not imply that deeper pipelines inherently benefit recovery-aware scheduling. Pipeline depth changes the amount, location, and composition of preserved in-flight state available at the selection point. The experiments therefore show that S3 produces consistently larger observed recovery gains in the evaluated five-stage organization. The microarchitectural conditions associated with this difference are examined further in the counterexample and failure analysis.

Task count shows a weaker pattern. The mean ΔR(4) is 0.2368 for N16 and 0.2780 for N32. However, N32 produces a larger gain than its matched N16 configuration in only 6 of the 20 pairs. The data therefore do not support a general claim that recovery-aware selection becomes more effective as task concurrency increases.

The two experimental families also remain positive on average. Family A produces a mean ΔR(4) of 0.2920, with 14 positive and six negative configurations, whereas Family B produces a mean ΔR(4) of 0.2229, with 18 positive and two negative configurations. This indicates that the observed S3 advantage is not confined to a single scheduler-equivalence structure.

9. Counterexample and Failure Analysis

S3 does not dominate S0 in every evaluated configuration. Eight of the 40 matched configurations exhibit a negative ΔR(4), and all eight occur in the four-stage organization. Four of these cases correspond to MatMult-Int, two to Dhrystone, and two to StateMate. CoreMark and CRC32 contain no negative S3–S0 configurations. The largest observed loss is −0.1173 retired instructions for Family A, MatMult-Int, N16, P4, while the remaining negative differences range from −0.0539 to −0.0131. The eight configurations in which S3 produces lower four-cycle recovery than S0 are listed in Table 7.

The event-level recovery traces provide additional information about these counterexamples. For each of the eight configurations, the corresponding P5 execution exhibits a higher mean S3 R(4) than its P4 counterpart. The increase is observed for both task counts and across all three affected workloads. Figure 6 shows this comparison using only valid four-cycle recovery windows from the final S3 campaign.

Across the eight counterexample configurations, the pooled mean S3 R(4) increases from 1.653 retired instructions under P4 to 1.910 under the matched P5 executions. More importantly, the composition of the recovery window changes. Complete four-instruction recovery, R(4) = 4, represents approximately 10.0% of the valid P4 recovery events in this subset and 23.4% of the corresponding P5 events. The increase is not uniform for every individual recovery class, indicating that the pipeline effect cannot be reduced to a simple shift of all recovery windows toward higher retirement counts.

The concentration of all negative S3–S0 results in P4 is consistent with differences in the recovery information exposed by the evaluated four-stage preserved state. This interpretation is compatible with the earlier rankability analysis, which showed that compact preserved-state descriptors do not encode recovery potential perfectly. C16 deliberately compresses the available state and therefore allows distinct microarchitectural situations to map to similar or identical descriptor values.

MatMult-Int provides the clearest workload-level warning. It accounts for four of the eight negative configurations and was also the most difficult workload for the richer preserved-state ranking model, with a workload-separated pairwise accuracy of 74.63%. This correspondence indicates that the preserved states observed for MatMult-Int were more difficult to order using the available pre-activation feature set. It does not establish that descriptor ambiguity is the sole cause of the four negative MatMult-Int configurations, but it identifies a consistent limitation across the discovery and policy-evaluation stages.

The available traces do not record the complete candidate set, the S0 fallback candidate, and the C16 score of every eligible context at each individual scheduling decision. Consequently, the eight configuration-level losses cannot be decomposed retrospectively into exact counts of beneficial and harmful S3 overrides without reconstructing information that was not emitted by the simulator. The failure analysis is therefore restricted to observable recovery outcomes and preserved-state characteristics rather than assigning an unverified causal classification to individual scheduler decisions.

This limitation does not affect the configuration-level comparison between S3 and S0. It instead defines the boundary of the mechanistic interpretation. The experiments show that the guarded policy substantially reduces unfavorable configurations relative to the less constrained recovery-aware policies, but the compact descriptor and one-point guard do not guarantee dominance over the deterministic baseline. The P4 counterexamples demonstrate that a recovery signal should remain subordinate to the primary scheduler and should be applied conservatively when the preserved state provides insufficient separation between eligible candidates.

10. Discussion and Limitations

The results show that preserved microarchitectural state can provide useful information for short-horizon recovery-aware scheduling, but only when the state is represented and consumed carefully. The comparison between S1, S2, and S3 demonstrates that increasing the amount of microarchitectural information available to the scheduler does not automatically improve the decision. The direct use of a richer descriptor can increase the number of unfavorable selections, whereas the guarded S3 policy limits the authority of the recovery signal and produces the strongest configuration-level behavior.

The evaluated recovery metric is intentionally local. R(H) measures the number of retired instructions within a short post-activation horizon and does not represent throughput, response time, worst-case execution time, worst-case response time, schedulability, deadline satisfaction, or fairness. The reported improvements therefore characterize immediate execution recovery after context activation rather than end-to-end real-time performance.

The C16 descriptor is also a deliberate approximation of the preserved microarchitectural state. It compresses stage occupancy, instruction class, dependency, and selected hazard information into a small representation suitable for scheduler-side use. The descriptor does not uniquely identify every possible preserved pipeline condition, and distinct states can therefore receive similar or identical recovery scores. The counterexamples observed in the four-stage organization are consistent with this limitation.

The experimental results are limited to the evaluated RISC-V simulation framework, five workloads, two pipeline organizations, two task-count levels, and the defined scheduler-equivalence structures. The consistent P5 advantage observed in the matched comparisons should not be generalized into a claim that deeper pipelines inherently improve recovery-aware scheduling. Pipeline depth changes the quantity and composition of preserved in-flight state, and the present experiments do not isolate these factors independently.

The analysis is based on simulator-generated timing and recovery traces rather than physical hardware measurements. No conclusions are made regarding implementation area, power, energy, maximum clock frequency, or hardware timing closure. The current traces also do not record the complete candidate set and C16 score of every eligible context at every decision point, which prevents a retrospective event-by-event classification of every S3 override as beneficial or harmful. In addition, C16 was derived from the observable state exposed by the evaluated preserved-context pipeline organizations. Although its constituent features represent generic pipeline properties, neither the selected bit allocation nor the scoring function is claimed to be optimal for other microarchitectures. Recalibration or redesign may therefore be required when the preserved-state topology changes substantially.

Future work should examine confidence-aware recovery scoring, descriptor aliasing, adaptive guard thresholds, and richer event-level instrumentation of scheduler decisions. A hardware implementation would also be required to quantify the cost of maintaining and evaluating the compact recovery descriptor.

11. Conclusions

This paper introduced a recovery-aware scheduling approach that treats preserved microarchitectural state as a secondary scheduling signal among contexts that are already equivalent under the primary scheduler. The objective is not to replace conventional scheduling policy, but to exploit execution progress that would otherwise remain invisible when several runnable contexts have the same scheduler-level preference.

A recovery metric based on short post-activation retirement was first used to determine whether preserved pipeline state contains enough information to distinguish recovery potential. The rankability analysis showed that recovery behavior is only partially captured by coarse occupancy information and that instruction-class, dependency, and hazard information contribute substantially to the prediction of short-horizon retirement. The offline compact-representation analysis characterized the rankability–complexity trade-off, while the deployed 16-bit C16 runtime descriptor was reconstructed and evaluated separately. The deployed C16 achieved 84.63% pooled and 86.81% unweighted macro pairwise ranking accuracy.

The scheduling study then evaluated a progression from deterministic selection to increasingly recovery-aware policies. The results show that descriptor richness alone is insufficient. Directly using preserved-state information can produce unfavorable selections, whereas the guarded S3 policy provides a more reliable mechanism by allowing the recovery signal to modify only otherwise equivalent decisions and only when a minimum score advantage is present.

Across the 40 matched configurations, S3 increases mean ΔR(4) by 0.2574 retired instructions relative to S0 and produces positive differences in 32 of 40 configurations. The corresponding mean improvements are 0.0801 for R(1) and 0.1561 for R(2). S3 is the best-performing policy in 29 configurations, while the remaining negative S3–S0 cases are confined to the four-stage pipeline. The evaluated five-stage organization produces a larger ΔR(4) than its matched four-stage counterpart in all 20 family–workload–task-count comparisons.

The counterexamples are important to the interpretation of these results. They show that preserved microarchitectural state is not automatically a reliable scheduling signal and that compact state representations can lose information relevant to immediate recovery. The value of preserved state therefore depends both on how it is represented and on how conservatively it is incorporated into the scheduler.

Preserved execution state can be transformed into a useful recovery-oriented scheduling signal without changing the authority of the primary scheduler. Its effectiveness depends on maintaining the distinction between scheduler eligibility and recovery preference, using a sufficiently informative compact representation, and constraining how that representation is allowed to influence context selection.