Short-Circuit Ruggedness of Schottky-Type p-GaN Gate HEMTs: A Review of Degradation Mechanisms, Failure Modes, and Chip-Level Hardening Techniques

1. Introduction

The relentless pursuit of higher switching frequencies and power densities in modern power electronics is continually approaching the intrinsic material limits of silicon-based devices, such as the breakdown electric field and carrier mobility [1]. Consequently, wide-bandgap semiconductors, particularly Silicon Carbide (SiC) and Gallium Nitride (GaN), have rapidly emerged in both commercial markets and academic research as promising alternatives for next-generation power conversion systems. Among them, GaN, owing to its wide bandgap (3.4 eV) and high electron saturation velocity, enables substantially higher switching speeds, conversion efficiencies, and power densities than conventional silicon devices [1,2,3]. To capitalize on these material advantages, the Schottky-type p-GaN gate HEMT has emerged as the dominant commercial GaN power-device architecture owing to its normally-off operation, excellent gate-drive compatibility, and low gate-drive losses. It has achieved widespread adoption in consumer electronics[4,5,6,7], and is now being actively pursued for industrial applications including data centers[8], photovoltaic inverters[9], and electric vehicles[10,11,12].Nevertheless, industrial power conversion systems impose stringent requirements on device reliability and long-term stability, with only limited parameter degradation being acceptable during operation. The present reliability performance of Schottky-type p-GaN HEMTs has yet to fully satisfy these demands, thereby hindering their large-scale deployment in high-reliability applications. In fact, SC ruggedness is widely acknowledged as one of the most critical figures of merit for power semiconductor devices. In practical high-power converter systems, an SC fault subjects the device to the simultaneous presence of high current and high voltage, constituting an accidental and extremely severe electrothermal stress. Three types of SC faults are commonly encountered: type-I hard-switching fault (HSF), type-II fault-under-load (FUL), and type-III flashover fault (FOF) [13,14,15]. In an HSF event, the device abruptly transitions from the OFF state to the SC state, as may occur in a half-bridge leg owing to an erroneous gate signal. In contrast, FUL results from a load-side failure while the device is conducting, whereas FOF is triggered by insulation breakdown within the power system, leading to exceptionally high di/dt and dv/dt transients [14,16]. These fault conditions can induce severe degradation or catastrophic failure, thereby jeopardizing the safe operation of the entire power system. Generally, the vast majority of reported studies have adopted the type-I HSF configuration for SC reliability evaluation because it provides a well-controlled drain-voltage stress, allows convenient gate-signal control and fault initiation, and closely emulates practical operating conditions. Moreover, experimental results reported by EPC indicate that the SC withstand capability does not differ significantly between HSF and FUL conditions [17]. To date, research on the SC ruggedness of p-GaN HEMTs has mainly focused on three areas: the attainable SC capability together with the associated failure modes and critical influencing factors [18,19,20,21,22,23,24,25,26,27,28,29,30], SC-induced degradation and the corresponding physical models [31,32,33,34,35,36,37,38,39], and chip-level SC hardening techniques [40,41,42,43,44,45,46]. However, a comprehensive review that not only summarizes these findings but also provides a unified perspective on the underlying reliability physics and their interrelationships is still lacking. Therefore, a systematic review of the SC ruggedness of Schottky-type p-GaN HEMTs is of both significant scientific interest and practical importance for the development and qualification of reliable GaN power devices. This paper is organized as follows. Section 2 reviews the SC withstand capability of Schottky p-GaN HEMTs under both single- and repetitive-pulse stress. The distinct failure modes associated with these two operating conditions are discussed. In particular, two representative thermal failure modes under single-pulse SC stress are compared, whereas repetitive SC stress is shown to generate substantial cyclic mechanical stress through thermal expansion and contraction of the GaN epitaxial layers. Section 3 addresses SC-induced instability and degradation. Monotonic shifts in threshold voltage (V_th) and on-resistance (R_on), typically observed in low-voltage devices, are attributed to electron trapping, whereas high-voltage Schottky p-GaN HEMTs exhibit unique nonmonotonic degradation due to the interplay between electron trapping and thermally enhanced hole injection. Section 4 surveys chip-level SC hardening strategies, including gate–source topology innovations and barrier, surface engineering approaches. Both conventional current-limiting techniques and recently developed adaptive protection concepts based on transient-gate-current-induced gate-voltage feedback are discussed, together with representative implementations in GaN and SiC power devices.

2. Short-Circuit Capability and Failure Mechanisms of Schottky p-GaN HEMTs

2.1. Short-Circuit Capability of p-GaN HEMTs

SC ruggedness is one of the essential reliability metrics for power devices in power conversion systems and is commonly evaluated in terms of both single-pulse and repetitive-pulse SC capability. For single-pulse SC operation, the Short-Circuit Withstand Time (SCWT) is the primary figure of merit. It is defined as the duration from the occurrence of a short-circuit fault to catastrophic device failure. Therefore, the SCWT must be sufficiently long to allow the protection circuitry to detect the fault and safely shut down the device before irreversible damage occurs, thereby ensuring the reliable operation of the power system. Consequently, a minimum SCWT of approximately 10μs under a 400-V DC bus has become a widely accepted benchmark for 650-V-class power devices [18]. In addition to single-pulse capability, repetitive SC endurance is another key metric for evaluating SC capability. It is commonly quantified by the maximum number of SC cycles that a device can survive under specified SC conditions. State-of-the-art commercial Si IGBTs, for example, can typically withstand more than 1000 repetitive SC cycles with a pulse width of 10μs [45,46,47]. Such repetitive SC capability is also significant for improving system robustness by tolerating multiple accidental SC events throughout the converter lifetime.

Owing to their unique gate structure and polarization-induced 2DEG conduction mechanism, the SC behavior of GaN HEMTs differs distinctly from that of conventional Si power devices. Consequently, the reliability theories established for Si devices cannot be directly applied to GaN HEMTs, motivating extensive studies on their SC behavior and capability. Table 1 summarizes selected published experimental studies on the short-circuit withstand capability of commercial 650-V GaN HEMT. The included studies cover both depletion-mode (D-mode) and p-GaN gate enhancement-mode (E-mode) devices, as well as both single-pulse SCWT and repetitive short-circuit reliability characterization. Non-commercial devices and purely simulation-based studies are outside the scope of this table. It can be seen that commercially available GaN HEMTs generally exhibit a very limited SC capability. For single-pulse, Similarly, repetitive-pulse SC capability of GaN HEMTs remains severely limited. As listed in Table 1, both 650 V p-GaN gate HEMTs failed at merely the second SC pulse under V_DS = 400 V and V_GS = 6 V, irrespective of whether the single-pulse duration was 1μs [27] or 10μs [31]. This repetitive SC capability is markedly inferior to that of Si IGBTs. To further elucidate the factors governing SC capability, some studies have systematically also investigated the influence of different SC stress conditions. Experimental results consistently demonstrate that the SC capability is primarily affected by the drain bias V_DS [18], gate bias V_GS [18,33], external gate resistance R_G [26], and the peak short-circuit current I_{ds, peak} [24] during the SC event. Specifically, for 650-V GaN HEMTs, the SCWT decreases drastically from >20μs at V_DS = 250 V to <0.5μs at V_DS = 400 V, identifying the drain bias as the most critical factor [18]. Reducing V_GS from 6 V to 4 V enables the device to withstand a 10-μs SC stress at a 400-V bus voltage, confirming the effectiveness of lowering gate overdrive in limiting SC current [34]. In terms of gate resistance, increasing R_G from 10 Ω to 47 Ω extends the single-pulse SCWT of p-GaN HEMTs from 630μs to 982μs (a 56% improvement) [26]. Moreover, a negative correlation between the I_{ds, peak} and SCWT has been established, revealing that devices with the lowest I_{ds, peak} exhibit the longest SC endurance [24]. These observations consistently indicate that the SC capability is fundamentally determined by the electrothermal energy accumulated during the SC event. Based on these observations, the underlying SC failure mechanisms under both single-pulse and repetitive-pulse stress have been systematically investigated. These studies establish the fundamental physical basis for understanding SC failure and provide theoretical guidance for improving the SC ruggedness of GaN HEMTs.

2.2. Thermal Runaway and Material Melting Driven By Single-pulse SC Tests

Schottky-type p-GaN HEMTs exhibit two distinct single SC failure modes, which differ significantly in dissipated energy (E_SC), SCWT, and damage morphology. The first mode typically occurs at relatively lower drain-source voltages and is characterized by a longer failure time, higher dissipated energy, and larger catastrophic chip-scale damage. In contrast, the second mode is triggered at higher drain-source voltage, resulting in a much shorter time-to-failure, lower E_SC, and highly localized damage beneath the source field plate near the drain-side gate edge. Despite these distinct failure characteristics, both modes are fundamentally governed by the same thermal criterion: the local device temperature exceeds a material-dependent critical threshold during short-circuit operation. [19,20,22].

For the high-voltage failure mode, however, the critical temperature is reached through highly localized electrothermal overstress rather than global heat accumulation. The failure waveform is shown in Figure 1, this failure mode is characterized by an ultrashort failure time (<1μs), a low E_SC of only a few millijoules, yet an extremely high transient power approaching 10 kW under V_GS≥ 4.5V and V_DS ≥300 V [20]. Figure 2 presents the corresponding failure morphology at progressively higher magnifications. The decapsulated device shown in Figure 2a reveals only a small damaged region near the drain side, while the enlarged views in Figure 2b and Figure 2c further confirm that the damage is confined beneath the source field plate adjacent to the drain-side gate edge, indicating a highly localized thermal failure. Consistently, failure analysis and TCAD simulations reveal that the maximum lattice temperature is always concentrated at this location, as illustrated in the TCAD simulation results shown in Figure 3. The localized failure originates from the coupling of electric-field and current-crowding effects. Under high-drain short-circuit bias, pronounced electric-field peaks develop at the drain-side gate edge, while the electron current density increases significantly within the narrow channel beneath the source field plate and gate filed plate. Furthermore, the asymmetric chip layout aggravates current crowding at the chip level, reducing the effective active area by approximately 8% at V_DS = 360 V and 15% at V_DS = 485 V (V_GS = 4.5 V) [22]. The resulting ultrahigh local power density rapidly drives the junction temperature beyond the critical thermal limit of the GaN/AlGaN heterostructure, ultimately leading to catastrophic failure.

In contrast, under low drain-voltage conditions, the longer SC duration results in substantially higher energy dissipation, making global heat accumulation the dominant failure mechanism [26]. The failure waveform is shown in Figure 4. For example, at V_DS = 250 V and V_GS=5V, the device fails after about 380μs with a calculated energy of about 260 mJ, and the junction temperature is estimated to reach about 525 °C [20]. The resulting failure morphology is illustrated in Figure 5. As shown in Figure 5a, two large melted regions are observed near the drain metallization, indicating severe chip-level thermal damage. The enlarged views in Figure 5b further reveal that Region A extends vertically over approximately 200μm, while Region B exhibits a lateral width of about 70μm [19]. Unlike the localized failure observed under high drain bias, this failure mode originates from global heat accumulation throughout the device. Owing to the relatively high thermal resistance of the buffer layer [22], the generated heat cannot be efficiently dissipated during the prolonged SC stress. Meanwhile, chip-level current nonuniformity causes preferential heat generation near the drain metallization [20], where the temperature eventually exceeds the melting point of the surface metal. Consequently, extensive metallization melting and large-area thermal damage are induced, ultimately leading to catastrophic device failure.

2.3. Electrothermal Cumulative Failure Under Repetitive SC Stress

Compared with single-pulse SC failure, repetitive SC failure follows a distinct thermomechanical degradation process before catastrophic thermal failure occurs. Although both failure modes ultimately result in thermal destruction, repetitive SC failure is induced by the cumulative effect of cyclic electrothermal stress rather than a single extreme thermal event. Consequently, the repetitive SC ruggedness of p-GaN HEMTs is significantly inferior to their single-pulse SC ruggedness, with device failure occurring after substantially lower cumulative dissipated energy. Experimental investigation in [24] revealed that repetitive SC failure is governed by a cumulative dissipated-energy threshold rather than a fixed number of SC cycles. For the investigated 650-V Schottky-type p-GaN HEMT, failure occurred after only two repetitive SC pulses under V_DS=400 V and V_GS=5V, and a pulse width of 500 ns, corresponding to a cumulative dissipated energy of approximately 20 mJ[24].

The irreversible failure of p-GaN HEMTs under repetitive SC stress originates from a progressive thermomechanical degradation process induced by cyclic electrothermal loading. Owing to the unique GaN-on-Si heterostructure, the transition layer and SiN passivation layer possess substantially lower thermal conductivity than the AlGaN/GaN epitaxial layers [27,28]. Consequently, the heat generated during each SC pulse is confined within the thin GaN channel and buffer region, producing a pronounced transient temperature spike (Figure 6). Rather than directly triggering catastrophic thermal failure as in single-pulse SC events, the repeated temperature rise and subsequent cooling during successive SC cycles induce cyclic thermal expansion and contraction within the heterostructure, resulting in the gradual accumulation of thermomechanical stress as confirmed by the simulated stress distribution in Figure 7. The resulting thermomechanical stress progressively initiates and propagates thermal-fatigue cracks at the interface between the GaN buffer layer and the transition layer. As the cyclic thermomechanical stress accumulates, thermal-fatigue cracks are progressively initiated and propagated at the mechanically vulnerable interface between the GaN buffer layer and the transition layer [27,28]. As illustrated in Figure 8a, cracks develop between the second field-plate edge and the drain electrode after repetitive SC stress. The cross-sectional image in Figure 8b further reveals that the crack center is located precisely at the GaN buffer layer–transition layer interface, confirming that cyclic thermomechanical fatigue is the dominant physical origin of structural degradation. The progressive structural degradation further deteriorates the thermal dissipation capability of the device. Transient thermal-resistance characterization [29] indicates that the combined action of large temperature gradients and electrical stress promotes the generation of dislocations within the nucleation and buffer layers. The accumulated defects increase the thermal boundary resistance and overall thermal impedance, thereby suppressing vertical heat dissipation. Consequently, an increasing fraction of the generated heat remains confined within the active region during subsequent SC cycles, leading to progressively higher junction temperatures. The aggravated heat accumulation further accelerates thermomechanical degradation, establishing a self-reinforcing electrothermal feedback loop that ultimately culminates in premature thermal runaway and catastrophic device failure.

3. Degradation Under Repetitive Short-Circuit Stress

The previous section focused on the failure mechanisms of Schottky-type p-GaN HEMTs under single-pulse and repetitive SC stress. Besides possessing sufficient SC withstand capability, power devices must also maintain stable electrical characteristics during repetitive SC events to ensure the long-term reliability and safe operation of power conversion systems. However, repetitive electrothermal stress inevitably induces gradual electrical parameter degradation, particularly in the V_th, drain saturation current (I_DS) and R_on. Such electrical instability degrades the gate-drive margin, increases the conduction and switching losses, and ultimately compromises system reliability. Accordingly, extensive studies have investigated the evolution of electrical parameters under repetitive SC stress and established the corresponding degradation mechanisms. This section reviews the repetitive SC degradation behavior, the associated electrical instability, and the underlying physical mechanisms.

3.1. Electrical Instability Under Repetitive SC Stress

The repetitive SC stability of p-GaN HEMTs is also commonly evaluated using a hard-switching SC test platform. The test circuit and corresponding gate-drive timing are illustrated in Figure 9. During the evaluation, repetitive SC pulses are applied while ensuring that the device operates within its short-circuit safe operating area (SCSOA). An SC stress–electrical characterization–SC stress methodology is generally adopted, in which the repetitive SC test is periodically interrupted to characterize the electrical parameters of the device using a semiconductor parameter analyzer (e.g., Keysight B1505A). The degradation of key electrical parameters, including the V_th, R_on, is then monitored as a function of SC stress conditions and SC cycle count. Existing studies indicate that the electrical instability of p-GaN HEMTs under repetitive SC stress can generally be classified into two categories. The first is monotonic degradation, which is predominantly reported in low- and medium-voltage devices (rated at 100V), where the degradation continuously accumulates with increasing SC stress level and cycle count. The second is non-monotonic bidirectional degradation, which has recently been observed mainly in high-voltage p-GaN HEMTs (rated at 650V). The following sections review these two degradation behaviors and their underlying physical mechanisms.

Previous systematic studies have revealed a monotonic degradation behavior in low-voltage p-GaN HEMTs under repetitive SC stress. As shown in Figure 10, the V_th increases monotonically and the R_on similarly exhibits an upward trend with increasing SC cycle count, V_GS, and V_DS [35]. Notably, the most pronounced degradation generally occurs after the first SC event, followed by a progressively saturated evolution with further SC cycling. Moreover, increasing the SC stress severity, including higher V_GS and V_DS, leads to larger positive V_th shifts, greater R_on degradation, indicating a strong correlation between electrical parameter degradation and SC stress intensity. Similar monotonic degradation characteristics have also been observed in high-voltage p-GaN HEMTs under relatively mild SC stress conditions [31], suggesting that the same degradation mechanism dominates when the electrothermal stress remains limited.

In contrast to the monotonic degradation observed in low-voltage devices, high-voltage Schottky-type p-GaN HEMTs have recently been reported to exhibit a distinctly non-monotonic degradation behavior under repetitive SC stress [31]. As shown in Figure 11, the electrical parameters initially follow the conventional positive degradation trend but gradually reverse with increasing SC count and higher V_DS, V_GS. Specifically, V_th first shifts positively after the initial SC events and subsequently drifts in the negative direction with continued SC cycling, accompanied by a significant attenuation of the R_on degradation. For example, under relatively mild SC stress (650V device, V_GS = 4 V, V_DS = 100 V), ΔV_th reaches approximately +0.69 V after 10 SC cycles. However, under higher SC stress (650V device, V_GS = 6 V, V_DS = 300 V), ΔV_th decreases to only 0.04 V after 100 SC cycles, while the increase in R_on is reduced to merely 3% [31]. Such bidirectional parameter evolution suggests that the degradation mechanism of high-voltage p-GaN HEMTs fundamentally differs from the monotonic degradation observed in low-voltage devices.

3.2. Physical Mechanisms of V_th and R_on Degradation

During a SC event, the p-GaN gate HEMT simultaneously withstands a high bus voltage and a large current, so that two extreme physical conditions coexist inside the device: localized high peak electric fields at the drain-side gate edge and the field-plate edge, and severe self-heating caused by the rapid dissipation of the E_sc. These two conditions respectively drive two carrier-trapping processes of opposite polarity: field-assisted hot-electron trapping accumulates net negative charge in the gate stack and the drift region, leading to a positive drift of the V_th and an increase in the on-resistance R_on; whereas thermally enhanced hole injection introduces positive charge into the AlGaN/GaN heterostructure, neutralizing the negative-charge accumulation in the gate stack and thereby weakening or even reversing the V_th drift; concurrently, the elevated junction temperature suppresses hot-electron generation and electron trapping, alleviating the degradation of R_on. Their competition gives rise to the distinctive non-monotonic instability of V_th and R_on with SC stress intensity in 650 V Schottky-type p-GaN gate HEMTs [31].

Under mild repetitive SC stress (for a 650 V device with V_DS < 100 V and V_GS < 4 V), the short-circuit energy is low and the self-heating is moderate; the localized high peak electric field is the fundamental driving factor of degradation. The physical picture is illustrated in Figure 12: the positive gate bias bends the energy bands of the gate stack downward, forming a high-density 2DEG in the channel; during the SC event, electrons are accelerated by the high peak electric field at the drain-side gate edge into hot electrons and spill over the channel; part of these hot electrons are captured by traps in the p-GaN/AlGaN gate stack, and the negatively charged occupied traps deplete the 2DEG, resulting in a positive drift of V_th. Meanwhile, the high electric field at the source field plate (SFP) edge assists the transfer of electrons from the 2DEG channel and their capture at the residual dielectric/AlGaN interface states, producing a virtual-gate-like effect that increases R_on [31]. The magnitude of degradation in this regime should not be overlooked: for 650V device at V_GS = 4 V and V_DS = 100 V, after 100 cycles V_th drifts from 1.27 V to 1.95 V and R_on increases by about 34.5%; even a single SC event can cause a +0.40 V V_th shift and an 11% increase in R_on, which is sufficient to significantly degrade the dead time and conduction loss in practical applications [31]. It is worth noting that, although earlier degradation studies on low-voltage (≤100 V-class) devices reported only monotonic positive drift, their mechanistic explanations can be uniformly incorporated into the mild-stress framework described above.

When the repetitive SC stress exceeds a certain critical intensity ( for a 650 V device with V_DS ≥100 V and V_GS>4 V), the degradation mechanism of the device undergoes an essential transition, as shown in Figure 13. In the hole-injection-dominated regime, a higher gate stress voltage (4 V < V_GS ≤ 6 V) triggers hole injection from the p-GaN layer into the AlGaN/GaN heterostructure at the source-side gate edge—where the electric field induced by the SC gate stress voltage points approximately perpendicularly toward the 2DEG channel, lowering the local valence-band barrier; by contrast, the drain-side gate edge is dominated by the high SC drain stress voltage, and the valence-band barrier is much higher, as comparatively shown in Figure 13a. At the same time, as show in Figure 14 the strong self-heating triggered by the SC event raises the junction temperature in the gate region considerably, and the elevated temperature effectively may activate the ionization of acceptors in the p-GaN layer, further amplifying hole injection. The injected holes are subsequently captured by traps in the AlGaN barrier layer and the GaN buffer, reducing the net negative charge stored in the gate stack.

4. Short-Circuit Hardening Strategies for Schottky p-GaN Devices

4.1. Current-Limiting Device Engineering for Short-Circuit Hardening

Since catastrophic SC failure in p-GaN HEMTs is primarily caused by excessive power dissipation and the resulting thermal runaway, one of the most established hardening strategies is to intrinsically suppress the SC current through structural engineering. This design philosophy has been widely adopted in Si and SiC power devices and has recently been extended to p-GaN HEMTs. By reducing the saturation drain current I_DS, the peak SC current I_ds,peak and the corresponding peak power dissipation are effectively suppressed, thereby mitigating thermal accumulation during SC events and significantly improving both the single-pulse SC withstand capability and repetitive SC reliability. Several structural designs have been proposed to realize this intrinsic current-limiting effect without relying on external protection circuits. Rather than introducing a single universal solution, these approaches modify different regions of the device to regulate channel conduction under SC conditions while maintaining acceptable on-state performance.

One representative approach is the Schottky source extension (SSE), which is is integrated into the source side of the device; Figure 15 presents the schematic structures of the conventional device and the proposed device and equivalent circuit of the p-GaN HEMT integrated with the SSE. Under low drain bias, the SSE functions equivalently as a small series resistance and exerts minimal suppression on channel conduction. However, as the V_DS increases, the potential at the SSE node (V_X) rises rapidly. Once V_X reaches the drain saturation voltage of the channel beneath the SSE, this region becomes pinched off and the extension behaves as a constant-current source. As a result, the saturation current decreases from more than 400 mA/mm in the conventional device to approximately 100 mA/mm in the SSE-integrated device, as shown in Figure 16. Consequently, the saturation drain current is intrinsically limited, thereby suppressing the peak SC current and instantaneous power dissipation. AS shown in Figure 17a–d, high-voltage pulse I_D–V_DS tests, which mimic SC events with a 5-ms pulse width and V_GS held at 6 V, reveal that the conventional device fails at 351 V, whereas the SSE device withstands drain voltages up to 679 V. Progressive SC-stress characterization further shows that the conventional device fails under repeated stresses at 300 V, while the SSE device endures cumulative stresses up to 700 V before failure. Moreover, under repetitive SC cycling tests at V_DS = 400 V, V_GS = 6 V, and 10-μs pulse width, the conventional device fails after only approximately 3,064 cycles, whereas the SSE device operates stably for 11,571 cycles. These results demonstrate that the SSE structure substantially enhances both the SC withstand voltage and the repetitive SC durability.

As shown in Figure 18a, another on-chip current-limiting technique involves inserting a second gate between the main gate and the drain and shorting it to the source. As shown in Figure 18b, when large drain current flows through the source resistance during an SC event, the potential at the location beneath the second gate in the channel rises, while the second gate remains at zero potential due to its direct connection to the source. A negative bias thus develops between them, which modulates the channel at that location and reduces the saturation drain current. The effectiveness of this current-limiting mechanism depends on the coupling between the second gate and the underlying channel. In the Schottky-type second gate formed by directly depositing metal on the AlGaN barrier layer, the saturation current is reduced to 25% of that of a single-gate device (Figure 19a); the MIS-type second gate achieves a less aggressive reduction to 68% of the single-gate saturation current (Figure 19b). By reducing the saturation current, this dual-gate structure suppresses the power density during SC transients, thereby enhancing the SC capability of the device.

As shown in Figure 20, extending the p-GaN region toward the drain to form an extended p-GaN ledge structure is also an effective approach to enhance the SC ruggedness of p-GaN HEMTs. This structure requires no additional gate electrode; its extension region acts as a field plate, reconstructing the electric field distribution at the gate edge. Under SC conditions, the pinch-off point shifts from the drain-side gate edge to the edge of the extended p-GaN region, causing some electrons to be prematurely injected into the buffer layer. The output characteristics are shown in Figure 21. This achieves an intrinsic self-limitation of the saturation current, with a measured reduction of 17.4% at V_GS = 6 V and V_DS = 8 V. The reduced saturation current directly suppresses the SC transient power density, thereby improving the SC withstand capability.

In addition to the gate-side and source-side structural modifications, as shown in Figure 22, depositing a source-shorted metal layer above a thin dielectric layer in the gate-drain access region—provides another route to SC hardening by suppressing the saturation current. This configuration constructs a cascode-like equivalent circuit that reduces the saturation current density by depleting the 2DEG beneath the access-region metal, thereby suppressing power dissipation during SC transients. As shown in Figure 23, the saturation current is reduced, which can benefit to a better short-circuit robustness. As shown in Figure 24, pulsed SC test results demonstrate that conventional devices fail at a SC voltage of merely 239 V, whereas the device with the voltage seatbelt can achieve 401 V. The core objective of this design is active management of the gate electrostatic boundary and current-limiting for SC, rather than conventional field-plate optimization.

4.2. Thin AlGaN-Barrier Engineering for Adaptive Short-Circuit Protection

Beyond structural current-limiting approaches, another promising strategy is to enhance SC robustness by regulating the effective V_GS during the SC transient. Unlike conventional current-limiting techniques, this approach actively suppresses the SC current through electrostatic feedback, thereby alleviating the inherent trade-off between SC capability and static device performance. It has been established that enhancing the transient gate current during SC stress can create a negative electrostatic feedback on V_GS [48,49]. This approach is more effective than relying solely on passive self-heating for suppressing SC current and mitigating thermal accumulation. In SiC MOSFETs, an embedded polysilicon diode (PSD) leverages temperature-dependent reverse leakage. The resulting drop in V_GS yields a theoretically unlimited SCWT according to TCAD simulations. In vertical GaN Fin-JFETs, elevated junction temperature T_j drives hole injection across the G–S p-n junction. The increased I_G produces a voltage drop across the RC-interface gate resistor, suppressing I_ds,peak. For p-GaN HEMTs, thin AlGaN-Barrier maybe offer a distinct pathway to realizing the same adaptive protection concept.

Recently, this concept was experimentally demonstrated in a 650-V Schottky-type p-GaN HEMT with a thin AlGaN barrier (~11 nm, versus ~19 nm in conventional devices) [44]. The thin barrier enhances the transient gate current during SC stress through two charge-migration processes: thermally activated 2DEG electrons surmounting the thin barrier toward the gate, and hot electrons tunneling through the barrier to recombine with injected holes under the high SC electric field. Despite the enhanced transient current, the static gate leakage remains at the ~μA level, and the on-resistance remains at ~89 mΩ (Figure 25), so normal device performance is not sacrificed. During SC events, the enhanced transient gate current flows through the external gate resistor R_G, and the resulting voltage drop adaptively reduces the effective V_GS from 6 V to ~3 V, partially pinching off the 2DEG channel and thereby suppressing the SC current, as illustrated in Figure 26a. As shown in Figure 26b, quantitative extraction shows that this V_GS-reduction mechanism accounts for up to 69% of the total SC current reduction, whereas in conventional devices the current reduction is dominated by self-heating (nearly 100% for DUT-B and 63–84% for DUT-A).

As shown in Figure 27a and b, the device achieves a record-long single-pulse SCWT of 629μs under 450 V, surpassing all previously reported GaN, Si, and SiC power devices in Figure 28a. For repetitive SC events, Figure 27c and d show that the device survives up to 12,000 cycles at pulse widths of both 10μs and 50μs without failure, achieving the repetitive SC capability among GaN HEMTs and SiC MOSFETs in Figure 28b. Such extraordinary SC robustness intrinsically originates from the enhanced transient-gate-current, which adaptively reduces the effective gate voltage to partially pinch off the 2DEG channel, rather than relying on the fully passive self-heating effect that conventional devices depend on to sustain the stress.

5. Conclusions

Schottky-type p-GaN gate HEMTs have emerged as the dominant architecture for enhancement-mode GaN power devices, but their limited SC ruggedness remains a key barrier to adoption in high-reliability industrial applications. This review systematically examines the SC reliability of Schottky-type p-GaN HEMTs across failure mechanisms, degradation physics, and chip-level hardening strategies. The key takeaways are as follows.

• SC failure in p-GaN HEMTs is fundamentally thermally driven and exhibits two distinct modes—high-voltage localized breakdown and low-voltage global thermal melting—both rooted in the local temperature exceeding a material-dependent threshold.
• Repetitive SC stress induces cumulative thermomechanical damage through cyclic thermal expansion and contraction, causing failure at substantially lower total energy than single-pulse stress.
• Electrical degradation under repetitive SC stress shows two regimes: monotonic positive V_th and R_on shifts under mild stress (hot-electron trapping), and non-monotonic bidirectional evolution under severe stress (competition between electron trapping and thermally enhanced hole injection).
• The competitive compensation mechanism between field-assisted hot-electron trapping and thermally activated hole injection provides a unified framework for understanding both the monotonic degradation of low-voltage devices and the non-monotonic behavior of high-voltage devices.
• Two hardening approaches have been developed: current-limiting structural engineering (Schottky source extension, dual-gate structures, p-GaN extended field plates, voltage seatbelts) and adaptive protection via transient-gate-current-induced gate-voltage feedback enabled by thin-AlGaN-barrier engineering.
• State-of-the-art hardened devices have achieved SC withstand times exceeding 500μs at 450 V and repetitive endurance of up to 12,000 cycles with 50-μs pulses, representing orders-of-magnitude improvement over conventional devices.