FOLD: A Framework for On-Device Line-Segment Detection on STM32 Microcontrollers

1. Introduction

Line segment detection (LSD) serves as a fundamental component in visual SLAM, structure-from-motion, and industrial inspection. Lines become particularly valuable in environments where point features are scarce. Point-line SLAM systems [1,2] have been shown to be markedly more robust than point-only pipelines in low-texture, man-made indoor scenes. Such scenes are typical of mobile robots and drones, platforms that would benefit considerably from performing detection on the device itself rather than streaming imagery to a remote host. Modern learned detectors achieve high accuracy, yet they assume graphics processors or, at best, mobile-class application processors [3,4,5]. Even the lightest reported model requires tens of megabytes of runtime memory [6]. MiLSD was recently introduced as a compact int8 line-segment detector sized explicitly for microcontroller memory budgets [7]. It reaches a structural average precision of ${\mathrm{sAP}}^{10}=24.1$ on the ShanghaiTech Wireframe benchmark within a $1$MB activation budget. As an algorithmic result, however, its execution on hardware had not been demonstrated prior to this work.

This work introduces FOLD, a reusable framework for deploying convolutional line detectors on STM32 microcontrollers, and measures it on real silicon at four distinct operating points. The first operating point is F-Clip-25k on the STM32F746, a $216$MHz Cortex-M7 with only $320$KB of SRAM. This establishes the lower end of the deployment envelope. The second is MiLSD on the STM32H7 family, a 280 MHz to $600$MHz Cortex-M7 with approximately $1$MB of SRAM and no hardware accelerator. Inference runs in int8 through CMSIS-NN [8]. The decoder is implemented as a lightweight on-chip post-processing pass. The third and fourth are NPLSD-H and NPLSD-M on the STM32N6, a Cortex-M55 paired with the Neural-ART NPU [9]. The accelerator is a convolution engine. Transformer-based detectors therefore derive no benefit from it. The two NPLSD variants are fully-convolutional, NPU-native detectors, one built on a dense HGNetv2 trunk and one on a depthwise MobileNetV2 trunk, whose every operator is mapped onto the accelerator. They give the N6 tier a measured speed-versus-accuracy choice. A final measurement leaves the STM32 envelope. LINEA-N, a $3.9$ M-parameter transformer detector, is deployed on an NVIDIA Jetson Xavier NX exactly as released and measured under the same protocol. This edge-GPU reference tier bounds FOLD from above and prices, in measured joules, the distance between an MCU-integrated NPU and a commodity GPU module.

The contributions of this paper are as follows:

• FOLD is introduced: a single free and reproducible deployment framework for line detectors on STM32, spanning export, int8 quantization, code generation, on-chip decode, and on-target measurement.
• The first on-device characterization of learned line-segment detection on a microcontroller is presented. It spans the no-NPU (H7) and NPU (N6) classes, bounded from above by a measured edge-GPU reference (LINEA-N on a Jetson Xavier NX). Measured metrics include flash, peak SRAM, per-layer latency, throughput, and estimated energy; on the GPU tier, board power is measured directly.
• A memory-layout finding is established: on-chip deployability is decided by the largest contiguous SRAM region, not the nominal SRAM total. This observation is generalized across four STM32H7 boards.
• Two NPU-class findings are measured on the STM32N6: int8 quantization, not graph convolutionality, is what engages the accelerator ($698\times$ and $233\times$ float-to-int8 speedups on two independent graphs); and parameter count predicts neither latency nor memory residency, since the $4.2\times$ smaller depthwise variant runs $3.6\times$ slower and spills to external RAM while the dense variant runs fully on-chip in real time.

The remainder of this paper is organized as follows. Section 2 reviews related work. Section 3 describes the target platforms. Section 4 presents FOLD itself. Section 5 details the three device deployments. Section 6 reports the measured results. Section 7 and Section 8 provide discussion and concluding remarks.

2. Background and Related Work

2.1. Learned Line-Segment Detection

End-to-end parsing of line segments has been pursued by a number of modern detectors. L-CNN [3] detects junctions and verifies candidate lines through a Line-of-Interest head. HAWP and its successor [4,10] incorporate a holistic attraction field. F-Clip [5] eliminates junctions entirely and predicts each line’s center, length, and angle in a single fully-convolutional stage. Transformer-based detectors have pushed accuracy further. Examples include LETR [11], DT-LSD [12] (which reports ${\mathrm{sAP}}^{10}=71.7$), and LINEA [13]. These models, however, come at a higher computational cost. On the efficiency front, M-LSD [6] was designed for mobile phones, and EM-LSD [14] is a recent lightweight design with $1.1$ M parameters. Both still require tens of megabytes of runtime memory and assume a GPU or mobile-class SoC. FOLD adopts the F-Clip representation (center, length, and angle) precisely because it is single-stage and fully convolutional. This property makes on-chip decode and quantized microcontroller execution tractable, including on a convolutional NPU.

2.2. Detectors Deployed in This Work

F-Clip-25k is a minimal variant of F-Clip with 25k parameters. It serves as a lower-bound baseline.

Table 1. Target microcontrollers. The last row is the edge-GPU reference tier, outside the STM32 envelope.

Device	Core	SRAM	Flash	NPU
STM32F746	M7 @216 MHz	320 KB	1 MB	—
STM32H7B3	M7 @280 MHz	1 MB (contig.)	2 MB	—
STM32H743	M7 @480 MHz	1 MB (frag.)	2 MB	—
STM32N6	M55 @800 MHz	∼4.2 MB	ext.	Neural-ART
Jetson Xavier NX	6×Carmel @1.4 GHz	16 GB LPDDR4x	16 GB eMMC	Volta GPU (384-core)

Table 1. Target microcontrollers. The last row is the edge-GPU reference tier, outside the STM32 envelope.

Device	Core	SRAM	Flash	NPU
STM32F746	M7 @216 MHz	320 KB	1 MB	—
STM32H7B3	M7 @280 MHz	1 MB (contig.)	2 MB	—
STM32H743	M7 @480 MHz	1 MB (frag.)	2 MB	—
STM32N6	M55 @800 MHz	∼4.2 MB	ext.	Neural-ART
Jetson Xavier NX	6×Carmel @1.4 GHz	16 GB LPDDR4x	16 GB eMMC	Volta GPU (384-core)

MiLSD [7] is an int8 fully-convolutional detector that adopts the F-Clip representation on a backbone of approximately $0.39$ M parameters. The backbone is sized to a 1 MB activation arena. MiLSD incorporates sub-pixel decoding, test-time augmentation, and a Line-of-Interest verification head. It achieves ${\mathrm{sAP}}^{10}=24.1$ on the Wireframe benchmark.

NPLSD-H and NPLSD-M are two NPU-native detectors built entirely from the Neural-ART operator set, one on a dense HGNetv2-B0 trunk and one on a depthwise M-LSD-tiny trunk. Their design, training, and accuracy analysis are given in a separate publication [15]; Section 5.3 states the properties relevant to deployment.

2.3. TinyML and On-Device Inference

On a microcontroller, the binding constraint is peak activation memory rather than parameter count [16,17]. Int8 quantization [18] and optimized integer kernels (CMSIS-NN [8]) have made convolutional inference feasible on Cortex-M class processors. The STM32N6 adds the Neural-ART NPU [9,19], a convolution-oriented accelerator. A vendor-provided compilation flow handles analysis, quantization, code generation, and on-target benchmarking. On the N6, it maps supported operators onto the accelerator. Section 4 names the exact tool versions used in this work. Standardized microcontroller inference benchmarks, such as MLPerf Tiny [20], typically cover keyword spotting, image classification, anomaly detection, and person detection. These are lightweight tasks with scalar or low-dimensional outputs. Line-segment detection is substantially heavier. It produces a dense, structured output over the full image grid. Its on-device cost is therefore not captured by existing benchmark suites. This gap is part of what motivates the measurement study reported in this paper.

3. Target Platforms

Table 1 lists the STM32 devices covered in this work. The STM32F746 [21] is the most constrained device with $320$KB of SRAM. It hosts the 25k-parameter baseline. The STM32H7 line provides roughly an order of magnitude more SRAM, which enables MiLSD. As discussed in Section 5, however, placement is determined by the contiguity of that SRAM rather than its total size. The STM32N6 adds the Neural-ART NPU [9], which enables the NPU-native NPLSD-H. None of the devices requires an external accelerator or host processor. One non-STM32 device completes the table: a Jetson Xavier NX module (six Carmel cores, a 384-core Volta GPU, and 16 GB of shared LPDDR4x) [22] stands in for the commodity edge-GPU class as the reference tier of Section 5.4.

4. The FOLD Framework

FOLD is identical across all devices and entirely free of licensing costs. The only hardware expense is the board itself. Training is performed off-device; the microcontroller runs only quantized inference. This follows the train-off / infer-on paradigm.

4.1. Export and int8 Quantization

Each trained model is exported from PyTorch to ONNX at a fixed input resolution. The recommended PyTorch-to-STM32 flow does not import a PyTorch-native quantized graph directly. The fp32 ONNX model is therefore quantized to int8 using ONNX Runtime static post-training quantization in the tensor-oriented QDQ format. Calibration is performed on a few hundred images from the Wireframe dataset. Models trained with quantization-aware training retain full-precision accuracy after int8 quantization. The quantization process reduces the weight size by approximately a factor of four. ST Edge AI Core v4.0.1 is used throughout. The int8 ONNX model is imported into ST Edge AI (X-CUBE-AI) [23], which analyzes the model, validates it against the ONNX outputs, and generates C code. On the STM32N6, the same tool maps supported operators onto the Neural-ART NPU.

4.2. On-Chip Inference and Decode

The generated runtime exposes the network as a single ai_network_run call. This call operates on an input buffer, an output buffer, and a single activation arena. Turning network outputs into line segments is handled by a small arithmetic post-pass that runs on the MCU after inference. For the F-Clip, MiLSD, and NPLSD outputs, the center map is first dequantized. A $3\times 3$ max-pool non-maximum suppression step selects center peaks above a confidence threshold. For each selected peak, the length and angle maps provide a half-vector $(\frac{\ell }{2}cos\theta ,\frac{\ell }{2}sin\theta )$, which yields the two endpoints. A one-dimensional parabolic fit refines each peak to sub-pixel accuracy. MiLSD’s Line-of-Interest verification head is a small per-candidate multilayer perceptron. It operates on features pooled along each line and is evaluated on-chip.

4.3. Measurement Methodology

Flash and peak-SRAM figures are obtained from the toolchain’s analysis report. On-target latency is measured on the physical boards through the toolchain’s validate-on-target flow [23]. Energy per inference is computed as power multiplied by latency. On the Jetson reference tier, board power is read from the module’s on-board sensor during sustained inference, so its energy cell is a measurement rather than an estimate. Accuracy figures (sAP) are the off-device values for each model. Deployment preserves accuracy up to int8 rounding effects. In practice, the on-target C model reproduces the fp32 ONNX output to a cosine similarity of $\ge 0.99999$. MiLSD is bit-exact, and NPLSD-H achieves cosine $1.000$. Code generation therefore introduces no measurable accuracy loss.

5. Device Deployments

5.1. MiLSD on the STM32H7B3 (No NPU)

MiLSD’s int8 backbone, with approximately $0.39$ M parameters, runs in int8 through CMSIS-NN without any hardware accelerator. The exported int8 backbone ($0.394$ M parameters) occupies 386 KB of flash. The analysis report gives a peak activation arena of 847 KB at a $256\times 256$ pixel input. This arena is dominated by the deep $64\times 64\times 128$ convolutions. A negative finding emerged concerning where that arena can reside. The peak requires two simultaneous activation buffers of approximately 512 KB each, corresponding to a convolution’s input and output. On the STM32H743 (480 MHz), the nominal 1 MB SRAM is split into separate domains: a 512 KB AXI-SRAM plus additional regions of at most 288 KB. Only one buffer of that size fits in any single contiguous region. The model therefore cannot be allocated on-chip. On a NUCLEO-H743ZI2, which has no external RAM, the model cannot be placed at all. On-chip deployability is thus determined by SRAM layout rather than total capacity. The STM32H7B3 resolves this issue. Its D1 domain exposes a single contiguous 1 MB AXI-SRAM. On an STM32H7B3I-DK, the 847 KB arena is placed entirely on-chip. Specifically, 768 KB reside in the AXI-SRAM at 0x24000000, and $64+15$ KB are placed in the DTCM. The board’s 16 MB external SDRAM is left unused. On real silicon, a single inference takes $10,614$ ms ($0.094$ FPS) at 280 MHz. The off-device ${\mathrm{sAP}}^{10}=24.1$ carries over unchanged. The estimated energy per inference is $1.18$ J (‡ in Table 6). Table 2 and Figure 1 generalize this observation across four STM32H7 boards. MiLSD runs fully on-chip only on the H7B3 with its contiguous 1 MB SRAM. It spills to external SDRAM on the memory-fragmented H747 and the small-internal H7S78. It cannot be placed at all on the NUCLEO-H743. Latency scales with clock frequency, from $10.6$ s at 280 MHz down to $5.2$ s at 600 MHz.

Table 2. MiLSD across four STM32H7 boards ($0.394$ M parameters, $256\times 256$ input, int8). All outputs match the ONNX model to cosine $1.00$.

Board	Core @ Clock	On-chip SRAM	Ext. RAM	Arena placement	Latency (ms)	FPS
STM32H7B3I-DK	M7 @280 MHz	∼1.2 MB (1 MB contig.)	16 MB	fully on-chip	$10,614$	$0.094$
STM32H747I-DISCO	M7 @400 MHz	1 MB (fragmented)	SDRAM	external (544 KB spilled)	$7,876$	$0.127$
NUCLEO-H743ZI2	M7 @480 MHz	1 MB (fragmented)	none	cannot place	—	—
STM32H7S78-DK	M7 @600 MHz	620 KB (455 KB usable)	16 MB	external	$5,229$	$0.191$

Table 2. MiLSD across four STM32H7 boards ($0.394$ M parameters, $256\times 256$ input, int8). All outputs match the ONNX model to cosine $1.00$.

Board	Core @ Clock	On-chip SRAM	Ext. RAM	Arena placement	Latency (ms)	FPS
STM32H7B3I-DK	M7 @280 MHz	∼1.2 MB (1 MB contig.)	16 MB	fully on-chip	$10,614$	$0.094$
STM32H747I-DISCO	M7 @400 MHz	1 MB (fragmented)	SDRAM	external (544 KB spilled)	$7,876$	$0.127$
NUCLEO-H743ZI2	M7 @480 MHz	1 MB (fragmented)	none	cannot place	—	—
STM32H7S78-DK	M7 @600 MHz	620 KB (455 KB usable)	16 MB	external	$5,229$	$0.191$

The on-chip H7B3 sustains $1.83$ cycles per MACC, compared to $1.93$–$1.94$ on the external-RAM H747 and H7S78. This represents a small penalty for executing activations off-chip.

5.1.1. Where the Cycles Go

Table 3 decomposes the $10.6$ s H7B3 inference by layer. The workload consists almost entirely of the five $3\times 3$ convolutions. The two deepest convolutions ($128\to 128$ at $64\times 64$) cost 604 MMACC each and take $4.18$ s apiece ($39.4\%$ each). With the third 128-channel convolution, these account for $94.6\%$ of both the multiply-accumulate operations and the wall-clock time. The kernel sustains $1.83$ cycles per MACC ($2.97\times {10}^9$ cycles at 280 MHz). Latency is therefore a near-linear function of MACC count. This is a compute-bound, roofline-limited workload with no accelerator. Beyond the 385 KB of int8 weights, the generated runtime adds only 25 KB of flash and $3.8$ KB of RAM.

5.2. The Lower Bound: F-Clip-25k on the STM32F746

At the small end of FOLD’s range, a minimal 25k-parameter F-Clip variant fits entirely within the STM32F746’s 320 KB SRAM. Its activation arena is 200 KB, and the external SDRAM is left unused. Inference runs in 679 ms ($1.47$ FPS) at 216 MHz. The on-chip output matches the ONNX model to a cosine similarity of $0.99999$. The workload profile is convolution-dominated, with the two deepest convolutions accounting for $65\%$ of the runtime. This operating point anchors the low end of the accuracy-cost frontier (Section 6).

5.3. NPLSD on the STM32N6 (Neural-ART NPU)

The most accurate line detectors currently available are transformer-based. LINEA-N, for example, achieves ${\mathrm{sAP}}^{10}=65.0$ [13]. A microcontroller equipped with an NPU would appear to be the natural platform for raising the on-device accuracy ceiling. For transformer detectors, however, this expectation does not hold. The reason is architectural. The Neural-ART is a convolution accelerator. A transformer detector’s non-convolutional operators have no accelerator primitive. These include the deformable GridSample at the core of line-attention, LayerNorm, the attention Softmax, and TopK/Gather for query selection. Such operations execute on the Cortex-M55. In addition, the decoder’s self-attention over $1,100$ queries alone exceeds the on-chip activation budget. In practice, only LINEA-N’s backbone is deployable, and it runs approximately $99\%$ in software with the NPU idle. The accelerator is therefore wasted on a transformer. What the same detector achieves on hardware built for it is measured in Section 5.4. Table 4 summarizes operator support across the deployment targets.

The NPLSD pair is deployed instead: two fully-convolutional, NPU-native detectors co-designed for the accelerator. NPLSD-H retains the convolutional HGNetv2-B0 backbone [24,25] and replaces the transformer encoder-decoder with a convolutional feature pyramid and an F-Clip dense head ($2.63$ M parameters, ${\mathrm{sAP}}^{10}=37.9$ warm-started, 35.9 in int8). NPLSD-M rebuilds the depthwise M-LSD-tiny trunk for the same head ($0.62$ M parameters, ${\mathrm{sAP}}^{10}=41.9$, 41.1 in int8). Every operator in both designs, convolution, ReLU or its bounded Clip form, addition, concatenation, nearest-neighbour resize, and max-pool, maps onto the Neural-ART NPU. Qualitative results are shown in Figure 3. The architectures and training procedures are detailed in the companion paper [15].

Deployment on an STM32N6570-DK follows the same FOLD toolflow, with a static-shape simplification and a stem-pad fold to satisfy the accelerator compiler. NPLSD-H reproduces its reference output on-chip to cosine $1.000$ (signal-to-noise ratio of 121 dB); the int8 binaries reproduce their quantized ONNX references to cosine 0.9974 (H) and 0.9991 (M), the expected int8 rounding scale. Code generation therefore introduces no measurable drift. The measured values are collected in Table 5. NPLSD-H has $2.63$ M parameters and $2.69$ GMACC at $320\times 320$ input resolution. Int8 quantization reduces the weights from $10.05$ MB (float) to $2.55$ MB. A key finding is that int8 quantization is what engages the accelerator. When left in floating point, the network compiles to a native-float graph of 109 epochs (93 software, 9 hybrid, and only 7 pure hardware). On-target measurement shows that $99.7\%$ of the runtime executes on the Cortex-M55 at $23.6$ s per inference, with the NPU essentially idle ($0.3\%$ of runtime).

The integer accelerator cannot execute float convolutions. This is the native-float fallback, not an NPU result. In float, the activation working set is $8.86$ MB. Only $2.65$ MB stays in internal SRAM, while $6.25$ MB spills to external hyperRAM. The weights occupy $10.05$ MB of external octoFlash. This echoes, on the NPU class, the same internal-versus-external placement pressure observed on the H7 family. Int8 removes it for the dense trunk. The quantized NPLSD-H runs in $33.736$ ms per inference ($29.6$ inferences per second), a $698\times$ speedup over its own float fallback, with $95.2\%$ of the runtime on the NPU and zero pure-software epochs (72 hardware, 6 hybrid). Its $2.70$ MB activation arena resides entirely in internal SRAM, with no external RAM traffic at all: the first configuration of this work to run fully on-chip on the N6. Figure 2 shows the compiled epoch mapping of all four configurations.

On the same board, int8 NPLSD-M completes an inference in $121.736$ ms ($8.2$ inferences per second) at a $99.7\%$ hardware share, 51 of 53 epochs pure hardware and none in software; its 20 Clip nodes execute on the accelerator, confirming the ReLU6 adaptation in silicon. The comparison between the two variants is instructive. Although NPLSD-M carries $4.2\times$ fewer parameters and $1.74$ against $2.70$ GMACC, it runs $3.6\times$ slower. Depthwise convolutions offer the MAC array little arithmetic intensity per byte moved, an effect compounded by $2.34$ MB of activations spilling to external hyperRAM. What the smaller model does win is storage and accuracy: 650 KB of flash ($3.9\times$ less) and ${\mathrm{sAP}}^{10}=41.1$ against $35.9$. On an NPU, parameter count predicts neither latency nor memory residency. The tier map of Section 6 therefore offers the N6 two operating points rather than one winner: NPLSD-H for real-time, fully on-chip operation, NPLSD-M for accuracy and minimal flash. In energy terms the tier change is two orders of magnitude: from an estimated $1.18$ J per inference on the H7B3 to roughly 8 mJ for NPLSD-H and 30 mJ for NPLSD-M on the N6 (‡ in Table 6).

Table 5. Measured values for NPLSD-H and NPLSD-M on the STM32N6570-DK. Float rows show the native-float fallback; int8 rows are the deployed configurations.

Quantity	NPLSD-H	NPLSD-M
Parameters	$2.63$ M	$0.62$ M
MACC ($320\times 320$)	$2.69$ G	$1.74$ G
float weights (ext. octoFlash)	$10.05$ MB	$2.40$ MB
float latency (fallback)	$23,561$ ms ($0.3\%$ NPU)	$28,340$ ms ($0.0\%$ NPU)
float epochs (SW/hyb/HW)	93/9/7	∼all SW (91 total)
float activation RAM	$8.86$ MB ($6.25$ ext.)	—
int8 weights (flash)	$\mathbf{2}.\mathbf{55}$MB	$\mathbf{0}.\mathbf{65}$MB
int8 on-NPU latency	$\mathbf{33}.\mathbf{736}$ms ($29.6$ inf/s)	$\mathbf{121}.\mathbf{736}$ms ($8.2$ inf/s)
int8 NPU runtime share	$95.2\%$	$99.7\%$
int8 epochs (HW/hyb/SW)	72/6/0	51/2/0
int8 activation RAM	$2.70$ MB, all internal	$5.02$ MB ($2.34$ ext.)
int8 fidelity (C vs. quant. ONNX)	cosine $0.9974$	cosine $0.9991$
Accuracy (int8, deployed)	${\mathrm{sAP}}^{10}=35.9$	${\mathrm{sAP}}^{10}=41.1$
Platform	M55 @800 MHz, Neural-ART NPU

Table 5. Measured values for NPLSD-H and NPLSD-M on the STM32N6570-DK. Float rows show the native-float fallback; int8 rows are the deployed configurations.

Quantity	NPLSD-H	NPLSD-M
Parameters	$2.63$ M	$0.62$ M
MACC ($320\times 320$)	$2.69$ G	$1.74$ G
float weights (ext. octoFlash)	$10.05$ MB	$2.40$ MB
float latency (fallback)	$23,561$ ms ($0.3\%$ NPU)	$28,340$ ms ($0.0\%$ NPU)
float epochs (SW/hyb/HW)	93/9/7	∼all SW (91 total)
float activation RAM	$8.86$ MB ($6.25$ ext.)	—
int8 weights (flash)	$\mathbf{2}.\mathbf{55}$MB	$\mathbf{0}.\mathbf{65}$MB
int8 on-NPU latency	$\mathbf{33}.\mathbf{736}$ms ($29.6$ inf/s)	$\mathbf{121}.\mathbf{736}$ms ($8.2$ inf/s)
int8 NPU runtime share	$95.2\%$	$99.7\%$
int8 epochs (HW/hyb/SW)	72/6/0	51/2/0
int8 activation RAM	$2.70$ MB, all internal	$5.02$ MB ($2.34$ ext.)
int8 fidelity (C vs. quant. ONNX)	cosine $0.9974$	cosine $0.9991$
Accuracy (int8, deployed)	${\mathrm{sAP}}^{10}=35.9$	${\mathrm{sAP}}^{10}=41.1$
Platform	M55 @800 MHz, Neural-ART NPU

5.4. The Reference Tier: LINEA-N on a Jetson Xavier NX

How much of the remaining accuracy gap is a hardware question rather than a modeling one? To answer it, the strongest detector family of Section 2 is measured one tier above the microcontrollers, on the cheapest hardware class that runs it natively. LINEA-N [13], a $3.90$ M-parameter transformer detector, is deployed on an NVIDIA Jetson Xavier NX module [22] exactly as released: fp32 PyTorch weights ($15.6$ MB), no quantization, no operator surgery, no co-design of any kind. The board runs its 20 W six-core profile with locked clocks.

A single $640\times 640$ inference takes $101.1$ ms (median; $9.9$ inferences per second) and peaks at 210 MB of GPU memory. Half precision brings no gain here ($105.2$ ms): the workload on this GPU is bound by kernel-launch overhead rather than arithmetic, so the deployed configuration stays fp32. Board power, read from the on-module sensor during sustained inference, is $13.26$ W against $4.42$ W idle. That works out to $1.34$ J per inference, the one energy cell in Table 6 that is measured rather than estimated.

Under the unified evaluation protocol of this work, the deployed graph reaches ${\mathrm{sAP}}^{10}=63.9$ ($57.7$/$63.9$/$66.8$ at the 5/10/15 thresholds), consistent with the published $65.0$, which we reproduce exactly under the authors’ own evaluation stack. Input resolution matters at this tier: feeding the same $256\times 256$ frames used by the microcontroller deployments costs about six points (${\mathrm{sAP}}^{10}=57.9$), since a 640-input transformer cannot recover detail the capture path never stored. The reference tier presumes a full-resolution camera pipeline.

The comparison with the N6 is the point of the exercise. LINEA-N buys $+22.8$ points of ${\mathrm{sAP}}^{10}$ over NPLSD-M with zero deployment effort. NPLSD-H remains $3.0\times$ faster in wall-clock terms and roughly $168\times$ more energy-efficient per inference (∼8 mJ against $1,341$ mJ). Figure 3 adds this tier as its fifth column.

Figure 3. Qualitative results on two Wireframe validation scenes (#12 and #170). Columns: ground truth (green), MiLSD (no-NPU), NPLSD-H and NPLSD-M (NPU class), and LINEA-N (edge-GPU reference). Detections densify from MiLSD (${\mathrm{sAP}}^{10}=24.1$) through NPLSD-H (35.9) and NPLSD-M (41.1) to LINEA-N (63.9). The STM32 columns are raw decoded predictions, reproduced on-chip without drift; the LINEA-N column is the deployed fp32 configuration on full-resolution input.

Figure 3. Qualitative results on two Wireframe validation scenes (#12 and #170). Columns: ground truth (green), MiLSD (no-NPU), NPLSD-H and NPLSD-M (NPU class), and LINEA-N (edge-GPU reference). Detections densify from MiLSD (${\mathrm{sAP}}^{10}=24.1$) through NPLSD-H (35.9) and NPLSD-M (41.1) to LINEA-N (63.9). The STM32 columns are raw decoded predictions, reproduced on-chip without drift; the LINEA-N column is the deployed fp32 configuration on full-resolution input.

6. Results

Table 6 presents the measured on-device cost for the four operating points. Table 7 positions these points on the accuracy-resource frontier. FOLD spans a $105\times$ range in parameter count, from 25k for F-Clip to $2.63$ M for NPLSD-H, across the no-NPU and NPU classes. Accuracy increases from ${\mathrm{sAP}}^{10}=10.6$ to $41.1$, while latency decreases from $10.6$ s on the H7B3 to $33.7$ ms on the N6. The Jetson reference row extends the ladder to ${\mathrm{sAP}}^{10}=63.9$ at $101.1$ ms and prices that step at $1.34$ J per inference, measured on the board.

Further comparisons across tiers reveal insights not immediately apparent from the headline figures. Relative to MiLSD on the H7B3, NPLSD-M achieves an $87\times$ reduction in latency while delivering a 17.0-point accuracy gain. NPLSD-H improves upon the F746 baseline by a factor of 20 in speed, with an accuracy increase of $+25.3$ points. Profiling the int8 NPLSD-H binary reveals that two fused hardware meta-epochs dominate the schedule, consuming $11.4$ ms and $8.8$ ms respectively, together accounting for 60% of the $33.7$ ms inference time. The bottleneck has shifted. On the H7, the runtime was dominated by two software convolutions. On the N6, it is concentrated in two accelerator epochs. Further performance improvements would therefore require restructuring those computational blocks rather than relying on a faster core.

Table 6. On-device cost of the four operating points, plus the edge-GPU reference (LINEA-N on Xavier NX). All cells measured on-target; ‡ denotes estimated.

Detector / Device	Params	Flash	Peak SRAM	Latency	Energy/inf.
F-Clip / F746	0.025 M	25 KB	200 KB	679 ms	$0.23$ J ‡
MiLSD / H7B3	0.39 M	0.38 MB	847 KB	$10,614$ ms	$1.18$ J ‡
NPLSD-H / N6	2.63 M	2.55 MB	2.70 MB	$\mathbf{33}.\mathbf{7}$ms	∼8 mJ ‡
NPLSD-M / N6	0.62 M	0.65 MB	5.02 MB	$121.7$ ms	∼30 mJ ‡
LINEA-N / Xavier NX	3.90 M	15.6 MB	210 MB (GPU)	$101.1$ ms	$1.34$ J (meas.)

Table 6. On-device cost of the four operating points, plus the edge-GPU reference (LINEA-N on Xavier NX). All cells measured on-target; ‡ denotes estimated.

Detector / Device	Params	Flash	Peak SRAM	Latency	Energy/inf.
F-Clip / F746	0.025 M	25 KB	200 KB	679 ms	$0.23$ J ‡
MiLSD / H7B3	0.39 M	0.38 MB	847 KB	$10,614$ ms	$1.18$ J ‡
NPLSD-H / N6	2.63 M	2.55 MB	2.70 MB	$\mathbf{33}.\mathbf{7}$ms	∼8 mJ ‡
NPLSD-M / N6	0.62 M	0.65 MB	5.02 MB	$121.7$ ms	∼30 mJ ‡
LINEA-N / Xavier NX	3.90 M	15.6 MB	210 MB (GPU)	$101.1$ ms	$1.34$ J (meas.)

Table 7. Accuracy versus device class. ${\mathrm{sAP}}^{10}$ on Wireframe for the deployed int8 configuration; latency measured on-target. The LINEA-N row is the deployed fp32 configuration on the Jetson reference tier.

Operating point	${\mathbf{sAP}}^{10}$	Latency	Device class
F-Clip (25k)	10.6	679 ms	MCU, no NPU (320 KB)
MiLSD (this work)	24.1	10,614 ms	MCU, no NPU (1 MB)
NPLSD-H (this work)	35.9	33.7 ms	MCU + NPU (N6)
NPLSD-M (this work)	41.1	121.7 ms	MCU + NPU (N6)
LINEA-N (reference)	63.9	101.1 ms	edge GPU (Xavier NX)

Table 7. Accuracy versus device class. ${\mathrm{sAP}}^{10}$ on Wireframe for the deployed int8 configuration; latency measured on-target. The LINEA-N row is the deployed fp32 configuration on the Jetson reference tier.

Operating point	${\mathbf{sAP}}^{10}$	Latency	Device class
F-Clip (25k)	10.6	679 ms	MCU, no NPU (320 KB)
MiLSD (this work)	24.1	10,614 ms	MCU, no NPU (1 MB)
NPLSD-H (this work)	35.9	33.7 ms	MCU + NPU (N6)
NPLSD-M (this work)	41.1	121.7 ms	MCU + NPU (N6)
LINEA-N (reference)	63.9	101.1 ms	edge GPU (Xavier NX)

Every footprint and latency cell in Table 6 is now measured on-target across all five operating points, including the Jetson reference row. Figure 6 plots the accuracy-cost frontier. Figure 7 shows the flash and RAM footprint of each operating point, and Figure 5 details where the N6 activations reside: the int8 NPLSD-H arena fits entirely in internal SRAM, while its float fallback and the int8 NPLSD-M spill to external hyperRAM.

6.1. A Level-by-Level Selection Strategy

A selection rule falls out of the frontier. The board family fixes the detector class; within a class, the binding application constraint fixes the variant. Entry parts of a few hundred kilobytes admit only F-Clip-25k, which recovers coarse scene structure and nothing finer. Megabyte-class parts split by memory layout rather than by clock: those exposing one contiguous region carry MiLSD fully on-chip, while fragmented parts of the same nominal capacity cannot place it at all and should be passed over regardless of frequency.

Where an NPU is integrated, the choice narrows to a pair. A latency target or a hard on-chip requirement selects NPLSD-H, an accuracy target or a tight flash budget NPLSD-M. Once an edge-GPU module is admissible the lower-level constraints vanish altogether and the strongest published detectors run as released, at two orders of magnitude more energy per inference. Table 6 and Table 7 carry the measured values behind each of these choices, and the FOLD tier map in Figure 4 shows the result.

Figure 4. The FOLD tier map. Each device class carries the strongest detector its memory and compute admit: F-Clip-25k on the 320 KB F746, MiLSD on the contiguous-SRAM H7B3, the two NPU-native NPLSD variants on the N6, and LINEA-N on the Jetson Xavier NX reference tier. All latencies and accuracies are measured on the deployed configurations.

Figure 4. The FOLD tier map. Each device class carries the strongest detector its memory and compute admit: F-Clip-25k on the 320 KB F746, MiLSD on the contiguous-SRAM H7B3, the two NPU-native NPLSD variants on the N6, and LINEA-N on the Jetson Xavier NX reference tier. All latencies and accuracies are measured on the deployed configurations.

Figure 5. Activation placement on the STM32N6. Float graphs overflow internal SRAM; int8 NPLSD-H fits entirely on-chip ($2.70$ MB), while int8 NPLSD-M spills $2.34$ MB to hyperRAM. Residency, not capacity, separates the $33.7$ ms and $121.7$ ms points.

Figure 5. Activation placement on the STM32N6. Float graphs overflow internal SRAM; int8 NPLSD-H fits entirely on-chip ($2.70$ MB), while int8 NPLSD-M spills $2.34$ MB to hyperRAM. Residency, not capacity, separates the $33.7$ ms and $121.7$ ms points.

Figure 6. Accuracy versus measured latency for the five deployed points (circles: STM32 in red, Jetson in amber). Accuracy rises as latency falls across device tiers. The two N6 points expose the trunk trade-off, and LINEA-N shows what an edge GPU buys in accuracy and energy (Table 6).

Figure 6. Accuracy versus measured latency for the five deployed points (circles: STM32 in red, Jetson in amber). Accuracy rises as latency falls across device tiers. The two N6 points expose the trunk trade-off, and LINEA-N shows what an edge GPU buys in accuracy and energy (Table 6).

Figure 7. Measured int8 flash (weights) and peak activation RAM per operating point (log scale). NPLSD-H runs from $2.55$ MB of flash with a $2.70$ MB arena held entirely in internal SRAM; NPLSD-M needs only $0.65$ MB of flash but spills $2.34$ MB of its $5.02$ MB arena to external hyperRAM (hatched).

Figure 7. Measured int8 flash (weights) and peak activation RAM per operating point (log scale). NPLSD-H runs from $2.55$ MB of flash with a $2.70$ MB arena held entirely in internal SRAM; NPLSD-M needs only $0.65$ MB of flash but spills $2.34$ MB of its $5.02$ MB arena to external hyperRAM (hatched).

7. Discussion and Limitations

The three findings of this study share a shape worth stating plainly: on both device classes, what decides the outcome is where data sits and in what format, not how large the model is. On the no-NPU class, two otherwise comparable $1$MB parts differ entirely in deployability because one exposes its memory as a single contiguous region and the other does not; capacity is the number on the datasheet, contiguity is the number that matters. On the NPU class, precision plays the same gatekeeping role: an integer accelerator cannot execute float convolutions, so a float graph falls back to the host core almost in full, and the same graph in int8 engages the array. Size, meanwhile, predicts little. The smaller variant is the slower one, because depthwise convolutions offer the MAC array little arithmetic intensity per byte moved and their activations spill off-chip. Choosing a trunk for an NPU is a placement and residency question before it is a parameter-count question.

Measuring the Jetson sharpens this picture rather than diminishing it. A commodity edge GPU lifts accuracy well beyond any microcontroller point with no co-design effort at all, yet each of its inferences spends about as much energy as a full MiLSD run on the H7B3. Where the power budget is milliwatt-class, the NPU tier is not an approximation of the GPU tier; it is the only option.

Several limitations should be acknowledged. The $10.6$s inference time of MiLSD on a no-NPU Cortex-M7 is far from real-time for this workload. Energy figures are estimated rather than measured directly, with the Jetson tier as the exception: its power is read from the on-module sensor. Accuracy figures are inherited from off-device evaluation. On-target confirmation is limited to numerical agreement with the reference graphs.

8. Conclusion

This paper has presented FOLD, a free and reproducible framework for deploying line-segment detectors on STM32 microcontrollers. FOLD was demonstrated end-to-end at four operating points: a 25k-parameter F-Clip baseline on a $320$KB STM32F746, MiLSD on a $280$MHz STM32H7B3 (both fully on-chip with no accelerator), and the NPU-native NPLSD pair on an STM32N6 whose operators map onto the Neural-ART accelerator. A fifth, reference deployment measures LINEA-N on a Jetson Xavier NX and closes the map from above.

Across these points, the int8 flash footprint ranges from $25$KB to $2.55$MB. Accuracy rises from ${\mathrm{sAP}}^{10}=10.6$ to $41.1$ on the STM32 tiers, and to $63.9$ on the GPU reference, and the N6 tier reaches $29.6$ inferences per second. Three key findings have been established. First, the same MiLSD model cannot be placed on the faster but memory-fragmented STM32H743. On-chip deployability is therefore determined by SRAM layout, not size. Second, transformer detectors do not benefit from a convolutional NPU. This is why the NPU points are co-designed convolutional detectors, and why the transformer is measured on the GPU tier instead. Third, int8 quantization is the switch that engages the accelerator. Once engaged, dense trunks buy speed and on-chip residency, while depthwise trunks buy accuracy per byte of flash.