From Moore's Law to the Volume-Inverse Law

Bo Hua Sun; Everett X. Wang

doi:10.20944/preprints202608.1596.v1

Submitted:

20 August 2026

Posted:

24 August 2026

You are already at the latest version

Abstract

For six decades Moore's Law has guided the semiconductor industry, but dimensional scaling is now meeting hard physical and economic limits. Here we argue that the post-Moore era needs a figure of merit anchored to physical invariants rather than to calendar time. We introduce the spatiotemporal efficiency $\Lambda = N f /(P V)$, combining transistor count $N$, clock frequency $f$, power $P$ and heat-dissipating volume $V$. Once the total switching power is accounted for, both $N$ and $f$ cancel and $\Lambda$ reduces to the device energy efficiency divided by volume. Because the thermal resistance of a three-dimensional stack grows linearly with height, $\Lambda$ falls as $1/V$—a relation we call the Volume-Inverse Law. Bounded by Planck's constant and the Landauer limit, it recasts the central competition of the post-Moore era as computation per unit volume, and predicts a finite optimal stacking height and a decisive shift toward energy-efficient, architecture-led design.

Keywords:

post-Moore era

;

spatiotemporal efficiency

;

Volume-Inverse Law

;

Landauer limit

;

dimensional scaling

Subject:

Computer Science and Mathematics - Hardware and Architecture

Introduction

In 1965, Gordon Moore observed that the number of transistors on an integrated circuit roughly doubled every 18 to 24 months [10]. Though never a physical law, this empirical projection became the “first principle” of the global semiconductor industry for over half a century—serving both as a technological roadmap and an economic promise: performance increases while costs decrease.

However, this trajectory is approaching its end. As processes enter the 2-nanometer era, dimensional scaling approaches fundamental atomic limits [11]. When transistor gate widths shrink to the scale of a dozen silicon atoms, quantum tunneling causes electrons to leak uncontrollably, severely degrading energy efficiency. Concurrently, economic costs have skyrocketed: an advanced 3nm fabrication facility now requires over $20 billion in investment [1]. NVIDIA CEO Jensen Huang declared in 2022 that “Moore’s Law is dead.” Scholars predict the effective end of Moore’s Law will occur within the 2025–2030 timeframe [1].

The question is no longer whether Moore’s Law will end, but what physical invariant will guide the industry thereafter. This paper seeks to answer that question by proposing a framework that can guide the industry much like Moore’s Law did, but within the constraints of the 3D era.

The Fundamental Dilemma of Moore’s Law: The Absence of an Invariant

To understand the necessity of a new paradigm, we must first dissect the structural weakness of Moore’s Law.

Moore’s Law is, at its core, an empirical fit—it describes what happened, not why it happened. Like Kepler’s laws describing planetary orbits without explaining their mechanical roots, Moore’s Law charts exponential growth in transistor density over time but anchors itself to no physical invariant. Its independent variable is time; its dependent variable is transistor density. Engineers race against the calendar to meet the “18-month doubling” target, yet cannot answer the fundamental question: When time is no longer a uniform variable, does this law still hold?

The arrival of physical limits shatters the assumption of uniform time. As transistor dimensions approach atomic scales, further spatial compression (minimizing

Δ x

) causes momentum uncertainty to surge, leading to uncontrolled energy dissipation (heating). Conversely, further temporal compression (minimizing

Δ t

) results in energy fluctuations that cause leakage and crosstalk. Beneath these phenomena lies a deeper physical constraint—the Heisenberg Uncertainty Principle:

Δ E \cdot Δ t \geq ℏ / 2, Δ p \cdot Δ x \geq ℏ / 2

(1)

This implies that space and time cannot be compressed independently and infinitely. Moore’s Law focuses solely on the single dimension of “spatial scaling.” When spatial compression approaches its limit, a roadmap based purely on “doubling transistor count” inevitably fails.

A Practitioner’s Perspective: The Historical Pattern of Overcoming Roadblocks

The claim that Moore’s Law is ending must be weighed against a sobering historical fact: it has been declared dead many times before, and each time engineering ingenuity revived it. One of us (E.X.W.) spent two decades in CMOS process and device development at Intel and witnessed this pattern firsthand.

The engine beneath Moore’s Law was never transistor count alone but Dennard scaling [9]—the transistor scaling law under which shrinking the feature size while proportionally reducing the supply voltage

V_{d d}

yielded, at roughly constant power density, simultaneous gains in switching speed and integration density. Through the single-core era, each new process node delivered higher clock frequencies almost for free.

That free lunch ended abruptly at the thermal wall. By the Pentium 4 generation, voltage scaling had effectively stalled while clock frequency continued to climb, so the power density of a physically small die grew faster than any air-cooled package could remove the heat. Frequency saturated near 4 GHz and the single-core roadmap collapsed. The industry’s answer was not to defeat the wall but to route around it: abandoning the pursuit of ever-higher single-thread frequency in favor of multicore parallelism. Moore’s Law—as a statement about transistors per chip—continued.

A second roadblock appeared inside the transistor itself. As the SiO₂ gate dielectric thinned to only a few atomic layers, direct quantum-mechanical tunneling of electrons through the gate became a first-order contributor to power consumption, injecting a leakage current that no circuit technique could suppress. The solution came from materials science: replacing SiO₂ with a hafnium-based high-k dielectric (introduced at Intel’s 45 nm high-k/metal-gate node in 2007), which restored the required gate capacitance with a physically thicker barrier and cut gate-tunneling leakage by orders of magnitude. Once again, Moore’s Law continued.

The lesson from the trenches is consistent: whenever a specific technical obstacle threatened the roadmap, engineers found a solution and scaling resumed. This history is precisely why proclamations of Moore’s Law’s death are, rightly, met with skepticism. Yet the same history sharpens the central question of this paper. Every one of those victories was won against an engineering constraint—a constraint with headroom, susceptible to a cleverer material, architecture, or process. The thermal wall was relaxed by parallelism; gate leakage was relaxed by a new dielectric. What we confront now is categorically different: limits set not by the current state of engineering but by physical invariants—Planck’s constant h and Boltzmann’s constant

k_{B}

. No material lowers h, and no architecture repeals the Landauer bound. The remainder of this paper argues that the post-Moore roadmap must therefore be anchored not to yet another clever fix, but to these immovable constants.

Existing Alternatives and Their Limitations

From Planar to Volumetric: 3D Stacking and Chiplet

The most intuitive extension is moving from two-dimensional planar chips to three-dimensional space. 3D IC technology vertically stacks multiple compute and memory dies, constructing a “skyscraper” of silicon. Industry reports indicate that 3D integration can achieve substantial increases in transistor density while maintaining energy efficiency advantages [5]. Vertical integration dramatically shortens data paths, alleviating the “memory wall” bottleneck.

Chiplet technology decomposes large monolithic dies into smaller chiplets that are heterogeneously integrated, achieving system-level performance breakthroughs. The common characteristic of these approaches is: abandoning extreme scaling of a single die in favor of system-level performance enhancement through three-dimensional spatial expansion.

However, 3D stacking is not a panacea. Vertical stacking leads to a multiplicative increase in power density, making heat dissipation a new bottleneck. It changes the mode of performance improvement—from “compressing area” to “expanding volume”—but still fails to answer the question: Where is the limit?

From Space to Time: Huawei’s Tau ( $τ$ ) Scaling Law

In May 2026, Huawei formally proposed the Tau (

τ

) Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS) [2]. This marks a significant introduction of an industry-level evolutionary principle in the global semiconductor arena.

The core of the Tau Scaling Law is the replacement of “geometric scaling” with “temporal scaling”.

τ

is the time constant in circuit theory (

τ = R C

), determining response speed, signal delay, and power consumption. The law targets system-level reduction of

τ

across devices, circuits, chips, and systems. Its key technique, “logic folding,” folds planar circuits into three dimensions, shortening interconnect lengths by 50%–80%, improving transistor density by 2–5×, boosting performance by 30%–100%, and reducing power consumption by over 40% [2]. Over the past six years, Huawei has designed and mass-produced 381 chips based on the Tau Scaling Law, with projections to achieve transistor density equivalent to a 1.4nm process by 2031 [2].

The Tau Scaling Law’s breakthrough lies in shifting the optimization target from “spatial dimensions” to “signal time.” Nevertheless, it remains an empirical law centered on a single variable (

τ

). It answers what to optimize, but not where the limit lies. It lacks an invariant—a quantity that remains conserved across scaling and process evolution-to anchor the boundary of development.

The Spatiotemporal Law: Reconstructing the Evaluation Framework with Invariants

Physical Invariants: Planck’s Constant h and Boltzmann’s Constant $k_{B}$

We posit that the ultimate constraints on semiconductor development arise from two fundamental physical constants: Planck’s constant h (and its reduced form ℏ) and Boltzmann’s constant $k_{B}$ .

The Heisenberg Uncertainty Principle originates from h—the quantum of action, the source of all quantum uncertainty. Every effective logic operation requires a minimum energy

E_{min}

related to the switching time

τ

:

E_{min} \cdot τ \sim h

. The history of semiconductor development is, in essence, the continuous optimization of the allocation between space (V) and time (t) under this invariant h.

Concurrently, Landauer’s principle imposes another constraint: erasing one bit of information dissipates at least

k_{B} T ln 2

of heat [3]. This implies computation is bounded not only by quantum limits but also by thermodynamic limits—an insurmountable boundary between power dissipation, temperature, and information processing rate.

Definition and Derivation of the Spatiotemporal Efficiency $Λ$

Based on the above analysis, we propose a system-level evaluation metric—Spatiotemporal Efficiency $Λ$ :

Λ = \frac{N \cdot f}{P \cdot V}

(2)

where:

N: effective total number of transistors in the chip or system;
V: effective heat-dissipating volume (cm³), defined as the physical volume of the chip stack that contributes to heat removal through the primary cooling surfaces. For a stack of n dies each of thickness $t_{d}$ and lateral area A, $V \approx n \cdot t_{d} \cdot A$ to first order, though effective volume may be modified by thermal spreading resistance;
P: steady-state power dissipation of the chip (W);
f: operating clock frequency (Hz).

To make this metric physically predictive, we express P in terms of fundamental device parameters. In the dynamic-power-dominant regime, the total switching power of a chip containing N transistors is

P = N α C_{load} V_{d d}^{2} f,

(3)

where

α

is the switching activity factor,

C_{load}

is the average switched capacitance per transistor, and

V_{d d}

is the supply voltage. It is essential that the transistor count N appear explicitly: the power a package must remove scales with the number of switching devices, not with a single transistor.

Substituting Eq. (3) into Eq. (2), both N and f cancel identically:

Λ = \frac{N f}{(N α C_{load} V_{d d}^{2} f) V} = \frac{1}{α C_{load} V_{d d}^{2} V} .

(4)

This is already a striking result. The metric can be rewritten as

Λ = \frac{1}{V} \underset{η_{E} = 1 / (α C_{load} V_{d d}^{2})}{\underset{︸}{(\frac{N f}{P})}} = \frac{η_{E}}{V},

(5)

where

η_{E} \equiv N f / P

is the computational energy efficiency (useful operations per joule), which for a fixed device technology and supply voltage is a constant set by

α C_{load} V_{d d}^{2}

, the energy dissipated per switching event. Neither raw transistor count nor clock frequency enters

Λ

on its own; only their ratio to power—the energy efficiency—does, and volume therefore emerges as the governing variable. Frequency has not become irrelevant: as the thermal analysis below shows, it is a dependent quantity fixed by the available thermal budget rather than a free lever for improving

Λ

.

Voltage-Frequency Coupling and Thermal Constraints

The maximum operating frequency of a CMOS circuit is constrained by the RC delay, which can be modeled as a function of supply voltage [6]:

f_{max} = \frac{{(V_{d d} - V_{t h})}^{γ}}{K \cdot V_{d d} \cdot C_{load}}

(6)

where

V_{t h}

is the threshold voltage,

γ

is the velocity saturation index (

1 \leq γ \leq 2

for modern devices), and K is a process-dependent constant.

Conversely, the thermal constraint imposes a maximum allowable power density determined by the package’s thermal resistance

R_{t h}

:

P_{max} = \frac{T_{max} - T_{amb}}{R_{t h}}

(7)

where

T_{max}

is the maximum junction temperature and

T_{amb}

is the ambient temperature.

For a 3D stack with n layers, the thermal resistance scales significantly with volume. Assuming a stack where each layer has thickness

t_{d}

and lateral area A, the total thermal resistance can be approximated as:

R_{t h} \approx \frac{n \cdot t_{d}}{k_{eff} \cdot A_{cross}} + \sum_{i = 1}^{n - 1} R_{int, i}

(8)

where

k_{eff}

is the effective thermal conductivity and

R_{int, i}

are thermal interface resistances. For large n, the interface terms become significant, and the dominant contribution scales linearly with the number of layers:

R_{t h} \propto n \propto V

.

Derivation of the Volume-Inverse Law

We now derive the scaling of

Λ

with V under the thermal constraint.

Key assumptions for the derivation: (i) The chip operates in the super-threshold regime (

V_{d d} ≫ V_{t h}

), where

V_{d d}

is constrained by noise margins and process requirements rather than being a free scaling parameter; (ii) The thermal resistance scales linearly with volume,

R_{t h} \propto V

; (iii) Dynamic power dominates, so the total switching power is

P = N α C_{load} V_{d d}^{2} f

; (iv) Transistor count scales linearly with the number of stacking layers,

N \propto n \propto V

.

First, consider operation at the thermal limit. The maximum power P is fixed by the thermal budget and scales inversely with volume due to the linear increase in

R_{t h}

:

P \propto \frac{1}{R_{t h}} \propto \frac{1}{V}

(9)

Second, the achievable clock frequency f at this thermal limit follows from equating the total switching power, Eq. (3), to the thermal budget, Eq. (7). Solving for f and using

N \propto V

together with

P_{max} \propto 1 / V

:

f = \frac{P_{max}}{N α C_{load} V_{d d}^{2}} \propto \frac{1 / V}{V \cdot V_{d d}^{2}} = \frac{1}{V_{d d}^{2} V^{2}} .

(10)

A critical insight arises here: in the super-threshold regime relevant to high-performance computing, the supply voltage

V_{d d}

is not a free scaling parameter. It is pinned near-constant by noise margins, process variations, and reliability requirements (

V_{d d} \approx const .

), and cannot be reduced arbitrarily without incurring exponential frequency penalties as the circuit enters the sub-threshold regime. With

V_{d d}

fixed, the thermal-limited frequency therefore falls quadratically with volume,

f \propto \frac{1}{V^{2}},

(11)

because a taller stack must both remove less heat (larger

R_{t h}

) and share that shrinking budget among more transistors.

Third, the transistor count N scales linearly with the number of layers:

N \propto n \propto V

(12)

The corresponding useful throughput is

N f \propto V \cdot V^{- 2} = 1 / V

: stacking more layers actually lowers the total operations per second delivered at the thermal limit, because the quadratic frequency penalty outruns the linear gain in device count. Finally, substituting Eqs. (9), (11), and (12) into the definition of

Λ

reproduces Eq. (4):

\begin{matrix} Λ = \frac{N \cdot f}{P \cdot V} & \propto \frac{V \cdot (1 / V^{2})}{(1 / V) \cdot V} \\ = \frac{1 / V}{1} = \frac{1}{V} . \end{matrix}

(13)

This confirms the Volume-Inverse Law:

\begin{matrix} Λ \propto \frac{1}{V} \end{matrix}

(14)

This result is striking: although the raw transistor count N grows linearly with volume, the efficiency

Λ

—useful throughput per watt per unit volume—degrades as

1 / V

. The thermal bottleneck forces the power budget to fall as

1 / V

and the clock frequency as

1 / V^{2}

, so even the useful throughput

N f

declines as

1 / V

. Adding silicon by stacking buys transistors that cannot all be clocked.

Summary of the Volume-Inverse Law

The derivation above shows that the Volume-Inverse Law

Λ \propto 1 / V

is the joint consequence of the scaling relations collected in Table 1 and illustrated in Figure 1(a). Two independent routes lead to it: directly, because

Λ = η_{E} / V

with a constant energy efficiency

η_{E}

(Eq. 5); and, at the thermal limit, because the falling throughput (

N f \propto 1 / V

) and the falling power budget (

P \propto 1 / V

) combine as

Λ = (N f) / (P V) \propto 1 / V

.

The physical implications can be summarized in three layers:

First, time is the manifestation, volume is the foundation. The nominal GHz value of a chip is essentially just the maximum operable frequency under given packaging heat-dissipation capacity and supply voltage. Frequency is a dependent variable; three-dimensional heat-dissipating volume is the independent constraint.

Second, voltage is the sole engineering lever.

Λ

is strongly dependent on the square of the supply voltage

V_{d d}^{2}

. The only evolutionary direction for future chips is to approach the sub-threshold voltage regime (

< 0.2

V), using the quadratic reduction in voltage to offset the energy efficiency degradation imposed by volume expansion, despite the accompanying frequency penalty.

Third, the curse of linear diminishing returns in 3D stacking. Even if chips are stacked into a “skyscraper,” the energy efficiency return per unit volume decreases linearly with stacking layers—the higher the stack, the smaller the marginal gain. Planck’s constant draws the absolute ceiling; humanity can never surpass this boundary, only seek the most elegant “spatiotemporal trade-off” at its edge.

Time Evolution and the Crossover from Moore’s Law

The Volume-Inverse Law is not a statement about transistor count over time, but about efficiency at a given volume. To relate it to Moore’s Law, we can estimate the crossover point: as long as the dominant scaling mechanism is area reduction (i.e., shrinking V per transistor), the traditional Moore scaling holds. Once 3D stacking becomes necessary to continue increasing N, the efficiency begins to degrade.

Let

λ

be the technology node feature size; then planar transistor density

\propto 1 / λ^{2}

, and chip volume scales with

λ

times the die area. Historically, Moore’s Law gave

N (t) \propto 2^{t / 2 years}

. The Volume-Inverse Law suggests that when N is increased by stacking, the efficiency drops. The transition occurs when the gain from stacking is offset by the voltage reduction required. Based on current trends, this crossover is expected around the 3nm–2nm node, consistent with industry projections [1].

Distinguishing Quantum and Classical Regimes

The two invariants h and

k_{B}

dominate in different regimes. For large feature sizes (

> 10

nm), thermal noise and Landauer’s limit are the primary constraints; quantum tunneling is negligible. As dimensions shrink below 10nm, quantum effects (tunneling, uncertainty) become increasingly important. In the deep sub-threshold region, both effects coexist.

A useful phase diagram places the operating region of typical chips on a plane of transistor density vs. power density; the Volume-Inverse Law applies across the entire region, but the specific scaling exponents may vary. In the classical regime,

Λ \propto 1 / (V_{d d}^{2} V)

; in the quantum-limited regime,

Λ

is further bounded by

1 / (h f V)

, making the inverse-volume dependence even more stringent.

Discussion: Implications and Predictions

Optimal 3D Stacking Height

Written in terms of the discrete layer count

n \propto V

(with

R_{t h}

denoting thermal, not electrical, resistance), the efficiency inherits the same inverse law,

Λ \propto \frac{N \cdot f}{P \cdot n} \propto \frac{n \cdot (1 / n^{2})}{(1 / n) \cdot n} = \frac{1}{n},

(15)

so

Λ

decreases monotonically with height: the minimal model contains no interior maximum, and on efficiency grounds alone a single layer is optimal. A finite optimum

n_{opt}

emerges once the benefits of stacking that this minimal model omits are restored—chiefly the shortening of global interconnects. Partitioning a planar design across n tiers reduces the average wire length as

1 / \sqrt{n}

[7,8], which raises the interconnect-limited clock frequency; the system throughput

N f

therefore rises while wiring is the binding constraint, and only begins to fall once the thermal-limited frequency of Eq. (11) (

\propto 1 / n^{2}

) takes over. The achievable throughput is the lower envelope of these two regimes and peaks at their crossover (Figure 1(b)). The location of that peak is set by where thermal resistance turns super-linear (interface layers begin to dominate) or where frequency degradation becomes exponential (the sub-threshold onset). Using thermal-interface-resistance data [5], this sweet spot falls between roughly 4 and 8 layers for current cooling technologies, beyond which efficiency drops sharply.

Economic Consequences

The diminishing returns of 3D stacking imply that the semiconductor industry will face a rising cost per unit performance gain. The Volume-Inverse Law provides a physical basis for the economic slowdown: further investment in fabrication facilities may yield only marginal improvements. This suggests a shift from “more transistors” to “more efficient use of transistors” through advanced architectures (e.g., in-memory computing, analog computing, and specialized accelerators) [4].

Connection to Information Density

Writing

Λ = I f / E

in terms of information density

I = N / V

and energy density

E = P / V

shows that, as volume grows, the attainable information density at fixed energy density falls—consistent with Landauer’s principle that more volume implies more entropy generation per bit.

Nonlinear Effects in Real Stacks

Our analysis assumed linear thermal resistance scaling. In practice, thermal interface resistance, hot spots, and coefficient of thermal expansion mismatches introduce additional non-linearities that may make the inverse-volume law even more pessimistic. For example, interlayer thermal resistance can be a significant fraction of total

R_{t h}

, and its dependence on pressure and surface roughness can cause super-linear growth with n [5]. This reinforces the conclusion that volume expansion is not a free lunch.

A New Coordinate System for the Post-Moore Era

Where Moore’s Law offered a single “North Star”—transistor density on a plane—

Λ

offers a successor figure of merit that folds throughput, power and volume into one number and applies uniformly across planar chips, 3D stacks, chiplets and domain-specific accelerators. It shifts the question from “how many transistors” to “how efficiently is each unit of volume used.” The resulting roadmap has three stages: near-term volumetric integration, choosing a stacking height near

n_{opt} \approx 4

–8; mid-term voltage-limited scaling, pushing

V_{d d}

toward the sub-threshold regime to exploit the

1 / V_{d d}^{2}

dependence of

Λ

; and long-term architectural specialization, where in-memory and analog accelerators raise the efficiency coefficient once

V_{d d}

and V are exhausted.

This reframing carries an industrial corollary. Value migrates from lithographic shrinking to system-level integration—advanced packaging, thermal-interface materials and heterogeneous integration—and rewards collaboration across physics, materials science and architecture to push

Λ

toward the Landauer limit. Moore’s Law promised “faster and cheaper”; the Volume-Inverse Law promises “efficient and sustainable.”

Limitations and Scope

Before concluding, it is important to state the scope and limitations of the proposed framework. The Volume-Inverse Law is derived under the following assumptions:

1.: Super-threshold operation: The analysis assumes $V_{d d} ≫ V_{t h}$ , where the supply voltage is constrained by noise margins and reliability rather than being a free scaling parameter. In the sub-threshold regime, the voltage-frequency relationship becomes exponential, and the scaling exponent of $Λ$ with respect to V may differ.
2.: Linear thermal resistance scaling: The model assumes $R_{t h} \propto V$ for the dominant contribution. Advanced cooling technologies (e.g., microfluidic cooling, interlayer thermal vias) or monolithic 3D integration with ultra-low interface resistance could alter this scaling.
3.: Dynamic-power dominance: Leakage power is neglected. At very low voltages (deep sub-threshold) or high temperatures, leakage contributions may become significant and modify the scaling behavior.
4.: Constant transistor density per layer: The law assumes each stacking layer has the same transistor density. Heterogeneous integration with varying densities across layers would require a more nuanced model.
5.: Conventional CMOS technology: The framework is developed for conventional CMOS-based digital logic. Emerging technologies (e.g., superconducting logic, optical computing, quantum computing) operate under fundamentally different physical constraints.

Within these bounds, the Volume-Inverse Law provides a robust physical limit for conventional 3D-stacked CMOS systems. The law should be viewed as a guiding physical bound rather than a universal empirical curve applicable to all computing paradigms. It identifies the fundamental trade-off space, allowing engineers to optimize within the constraints.

Conclusion: From Empirical Table to Fundamental Logic

Moore’s Law cannot simply be “replaced.” It is the semiconductor industry’s empirical table—a precise description of transistor growth that, like Kepler’s laws before Newton, lacks the physical invariants needed to explain why. When physical limits break the assumption of uniform time, that table loses its predictive power.

Spatiotemporal efficiency

Λ

, and the Volume-Inverse Law derived from it, constitute the semiconductor industry’s “fundamental logic.” Anchored by Planck’s constant h and Boltzmann’s constant

k_{B}

as invariants, it unifies all optimization directions—dimensional scaling, temporal compression, three-dimensional stacking, architectural innovation—within a single evaluation framework. It offers not an “18-month doubling” calendar promise, but a physical upper bound on “how much computation can be extracted per unit volume at the quantum-thermodynamic boundary.”

In the future, the industry will continue to speak of “equivalent nanometers,” just as astronomers still speak of “planetary orbits.” But the underlying coordinate system that determines the industry’s direction will shift from a “dimensional race” to a “volumetric efficiency race.” Moore’s Law defined the semiconductor industry’s adolescence—the era of competing over who grows faster; the Volume-Inverse Law will define its maturity—the era of competing over who lives most gracefully before the eternal physical invariants.

Predictions for the Industry

Based on our framework, we offer four concrete predictions:

1.: The optimal number of stacked layers in commercial 3D ICs will converge to 4–8, with further stacking showing negligible performance-per-watt improvement relative to the increased cost.
2.: Supply voltages will continue to decrease toward 0.2–0.3V, but performance gains (frequency scaling) will be modest as frequency scales inversely with thermal resistance.
3.: Architectural innovations (e.g., near-memory computing, analog processing, in-memory computing) will become more important than pure transistor scaling for continued efficiency improvements.
4.: The semiconductor value chain will pivot towards advanced packaging and thermal management, reflecting the shift from planar to volumetric constraints. Investment in packaging R&D will eventually exceed investment in front-end lithography.

Data Availability Statement

No datasets were generated or analysed for this Perspective; all quantitative relations are derived analytically in the main text.

Conflicts of Interest

The authors declare no competing interests.

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Figure 1. The Volume-Inverse Law. (a) Log–log scaling of the key quantities with heat-dissipating volume V (equivalently stack height

n \propto V

) at the thermal limit and fixed supply voltage: transistor count

N \propto V

, power budget

P \propto 1 / V

, and clock frequency

f \propto 1 / V^{2}

combine so that the spatiotemporal efficiency

Λ \propto 1 / V

(thick curve); the useful throughput

N f

shares the

1 / V

slope. (b) Origin of a finite optimal stacking height as the crossover of two competing mechanisms. Stacking shortens global interconnects—the average wire length of a design partitioned across n tiers scales as

1 / \sqrt{n}

[7,8]—which raises the interconnect-limited throughput (rising branch); meanwhile the thermal-limited throughput falls as

1 / n

(Eq. 11). The achievable throughput

N f

is the lower envelope of the two and peaks at their crossover, within the shaded

n_{opt} \approx 4

–8 band.

Figure 1. The Volume-Inverse Law. (a) Log–log scaling of the key quantities with heat-dissipating volume V (equivalently stack height

n \propto V

) at the thermal limit and fixed supply voltage: transistor count

N \propto V

, power budget

P \propto 1 / V

, and clock frequency

f \propto 1 / V^{2}

combine so that the spatiotemporal efficiency

Λ \propto 1 / V

(thick curve); the useful throughput

N f

shares the

1 / V

slope. (b) Origin of a finite optimal stacking height as the crossover of two competing mechanisms. Stacking shortens global interconnects—the average wire length of a design partitioned across n tiers scales as

1 / \sqrt{n}

[7,8]—which raises the interconnect-limited throughput (rising branch); meanwhile the thermal-limited throughput falls as

1 / n

(Eq. 11). The achievable throughput

N f

is the lower envelope of the two and peaks at their crossover, within the shaded

n_{opt} \approx 4

–8 band.

Table 1. Scaling of the key quantities with heat-dissipating volume V (equivalently, with stack height

n \propto V

) at the thermal limit, for fixed supply voltage

V_{d d}

.

Table 1. Scaling of the key quantities with heat-dissipating volume V (equivalently, with stack height

n \propto V

) at the thermal limit, for fixed supply voltage

V_{d d}

.

Quantity	Scaling	Origin
Transistor count N	$\propto V$	one device layer per unit height
Thermal resistance $R_{t h}$	$\propto V$	series conduction through the stack
Power budget P	$\propto 1 / V$	$P_{max} = Δ T / R_{t h}$
Clock frequency f	$\propto 1 / V^{2}$	fixed budget shared among N devices
Throughput $N f$	$\propto 1 / V$	linear gain vs. quadratic penalty
Efficiency $Λ$	$\propto 1 / V$	$Λ = η_{E} / V$

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From Moore's Law to the Volume-Inverse Law

Abstract

Keywords:

Subject:

Introduction

The Fundamental Dilemma of Moore’s Law: The Absence of an Invariant

A Practitioner’s Perspective: The Historical Pattern of Overcoming Roadblocks

Existing Alternatives and Their Limitations

From Planar to Volumetric: 3D Stacking and Chiplet

From Space to Time: Huawei’s Tau ( τ ) Scaling Law

The Spatiotemporal Law: Reconstructing the Evaluation Framework with Invariants

Physical Invariants: Planck’s Constant h and Boltzmann’s Constant k B

Definition and Derivation of the Spatiotemporal Efficiency Λ

Voltage-Frequency Coupling and Thermal Constraints

Derivation of the Volume-Inverse Law

Summary of the Volume-Inverse Law

Time Evolution and the Crossover from Moore’s Law

Distinguishing Quantum and Classical Regimes

Discussion: Implications and Predictions

Optimal 3D Stacking Height

Economic Consequences

Connection to Information Density

Nonlinear Effects in Real Stacks

A New Coordinate System for the Post-Moore Era

Limitations and Scope

Conclusion: From Empirical Table to Fundamental Logic

Predictions for the Industry

Data Availability Statement

Conflicts of Interest

References

From Space to Time: Huawei’s Tau ( $τ$ ) Scaling Law

Physical Invariants: Planck’s Constant h and Boltzmann’s Constant $k_{B}$

Definition and Derivation of the Spatiotemporal Efficiency $Λ$