A Fast-Transient LDO with Enhanced Level-Shifted FVF and Dynamic Compensation

1. Introduction

As X-ray imaging systems evolve toward higher frame rates, greater throughput, and higher levels of integration, detector readout ASICs typically integrate large-scale pixel arrays, multichannel analog front ends, analog-to-digital converters, and high-speed digital processing modules [1,2,3,4,5,6]. During data acquisition and readout, the simultaneous activation of numerous digital circuits and rapid switching between operating states can induce large and abrupt variations in the supply load current. The digital power-management circuitry of the ASIC must therefore provide a fast transient response while maintaining stable operation under such conditions. Meanwhile, the readout ASIC also imposes stringent constraints on the area and power consumption of the power-management circuitry. To address these requirements, this work presents an LDO implemented in a 130-nm CMOS process, operating from a 1.5 V input to provide a 1.2 V output with a 200 pF load capacitance. The proposed LDO achieves fast transient response and stable operation over a load-current range of 0–400 mA.

Conventional LDOs typically employ an Error Amplifier (EA) to drive the power transistor and regulate the output voltage through negative feedback, as illustrated in Figure 1. However, in high-load-current applications, the power transistor generally requires a large device size, resulting in substantial gate parasitic capacitance. This parasitic capacitance, together with the relatively high equivalent output resistance of the EA, results in a large gate charging and discharging time constant and consequently limits the load-transient response speed [7,8,9]. Therefore, accelerating the charging and discharging of the gate of the large power transistor and mitigating the transient-response limitation imposed by its parasitic gate capacitance are key challenges in achieving fast transient performance in high-load-current LDOs.

To address the aforementioned challenges, Flipped Voltage Follower (FVF)-based LDOs, as shown in Figure 2, have attracted considerable attention owing to their fast feedback path and low equivalent impedance [10,11,12,13]. In a conventional FVF, M₁ directly senses variations in the output voltage, while the current through M₂ modulates the current delivered by the pass transistor M_P, allowing load disturbances to bypass the slow feedback path associated with the bandwidth-limited conventional EA and thereby improving the transient response. However, conventional FVFs still suffer from two major limitations when operating over a wide load-current range. First, the gate voltage of the pass transistor M_P and the drain voltage of the control transistor M₁ are coupled; at light loads, $V_{\mathrm{PG}}$ must increase to reduce the overdrive voltage of $M_P$, which may force M₁ into the triode region and consequently cause a deviation in the output voltage. Second, the conventional FVF provides only small transient charging and discharging currents to V_PG, resulting in a limited slew rate at V_PG and consequently constraining the transient response speed.

To address the first issue, the shared node between the two branches can be decoupled [14,15,16,17]. Albezzano et al. [14] introduced a common-gate stage into the fast feedback loop to form a Cascoded FVF, which redistributes the internal node voltages and enables M₁ to maintain an appropriate operating condition over a wider load current range. However, the voltage level shift provided by this structure is relatively limited, approximately equal to the overdrive voltage of the common-gate transistor. To further increase the voltage level shift, a source follower can be employed [15] to form a Level-Shifted FVF (LS FVF). Under a small overdrive voltage condition, its DC voltage level shift can be approximately equal to the threshold voltage. Cai et al. [16] further modified the source follower in the LS FVF into a Super Source Follower (SSF), forming an SSF FVF, which achieves the same voltage level shift as the LS FVF while providing a lower output impedance. However, the SSF FVF requires the output pole to be located at a low frequency to ensure stability, which limits the maximum load current and imposes a minimum load capacitance requirement. To further extend the load current range, Zhu et al. [17] combined the Cascoded FVF and SSF FVF to develop a Buffered FVF (BFVF), which provides an enhanced voltage shift. However, this circuit exhibits degraded stability under no-load conditions. Considering that the application requires a wide load current range, including the no-load condition, the Cascode FVF, SSF FVF, and Buffered FVF structures are not adopted in this design. Instead, the LS FVF structure is employed.

To address the second limitation, the transient response can be improved by increasing the charging and discharging speed of the node of the pass-transistor gate [18,19,20]. Lu et al. [18] introduced dynamic biasing into the FVF to rapidly adjust the bias current of the FVF loop in response to load-current variations, thereby improving the transient response. In this scheme, a common-gate MOS transistor converts variations in the output voltage into current variations, which are then mirrored to modulate the FVF bias current, enabling rapid adjustment of the gate voltage of the large pass transistor and alleviating the gate slew-rate limitation inherent in fixed-bias implementations. However, the load-dependent variation of the internal poles in this topology is relatively complex, posing considerable challenges to stability design over a wide load-current range. To further improve the transient response, Boanloo et al. [19] employed a push–pull technique to enhance the gate slew rate of the pass transistor in the FVF. This approach employs cross-coupled common-gate branches to establish two output-voltage feedback paths. The resulting feedback signals control the push–pull stage to provide larger bidirectional charging and discharging currents, thereby mitigating the slew-rate limitation caused by the limited drive current in conventional FVFs. However, this method requires additional gain stages and signal paths, increasing the number of internal dynamic nodes and substantially complicating frequency compensation and stability design across the entire load range. In addition to the above approaches, Pappiah et al. [20] incorporated a Slew-Rate Enhancer (SRE) into an FVF LDO, where capacitive coupling senses variations in the FVF control voltage and dual current mirrors directly charge and discharge the parasitic gate capacitance of the pass transistor, thereby reducing the output-voltage deviation caused by load transients and shortening the recovery time. However, this design was validated over a narrow load-current range of 0–50 mA, and its transient driving capability for a large pass transistor under load currents of several hundred milliamperes has not yet been sufficiently demonstrated. Considering the stringent chip area constraint and the wide load current range of 0–400 mA in this application, the design combinates dynamic biasing, push-pull driving, and capacitive coupling techniques to enhance the transient response speed.

In addition, frequency compensation of the LDO over a wide load-current range represents another major design challenge, which can be addressed using techniques such as pole splitting, and dynamic compensation [21,22,23].

In summary, although numerous improvements to FVF-based LDOs have been proposed to extend the load-current range and enhance the transient response, several limitations remain. To meet the requirements of the digital power supply in X-ray detector readout ASICs for fast transient response and a wide load-current range, this work proposes an LDO based on an improved LS FVF architecture implemented in a 130-nm CMOS process, as shown in Figure 3. In the proposed design, the source follower in the LS FVF relaxes the coupling between the DC operating points and forms a fast local feedback loop, while its low output impedance enhances the capability to drive the gate of the large power PMOS transistor. Capacitive coupling is further employed to sense transient variations in the output voltage and dynamically adjust the LS FVF bias current, thereby providing the fast feedback loop with enhanced drive capability during load transients. Meanwhile, a positive-feedback auxiliary circuit is proposed to accelerate the transient response of the gate voltage of M_P. Moreover, to maintain stability over the entire load-current range, a dynamic pole-zero compensation scheme is adopted, in which the compensation network adjusts the pole and zero locations according to the load condition to accommodate variations in the system poles.

The remainder of this paper is organized as follows: Section 2 analyzes and designs the key modules, including the LS FVF fast loop, dynamic biasing circuit, positive feedback auxiliary circuit, and EA. Section 3 establishes a dual-loop small-signal model, analyzes the system poles and zeros as well as the dynamic pole-zero compensation mechanism, and presents the frequency-compensation design of the LDO. Section 4 presents the LDO layout and post-layout simulation results and compares its performance with prior work in terms of DC characteristics, load-transient response, Power-Supply Rejection Ratio (PSRR), and other key metrics. Finally, Section 5 concludes the paper.

2. Proposed LDO Architecture

2.1. LS FVF Fast Loop Analysis and Design

In this application, the current load varies from 0 to 400 mA, resulting in a wide variation in the gate voltage of the power transistor M_P. However, the biasing condition of the conventional FVF is difficult to accommodate such a wide gate voltage range, which may drive the control transistor M₁ out of the saturation region and degrade the normal operation of the feedback loop. To address this issue, a level shifter consisting of M_LS and M_LSP is incorporated into the FVF to form an LS FVF, as shown in Figure 4. By decoupling the gate of M_P from the drain of M₁, the proposed structure alleviates the a forementioned limitation and enables all transistors to maintain appropriate operating conditions over a wide load range. Furthermore, the source-follower-based level shifter introduced in the LS FVF further reduces the equivalent impedance at the gate node V_PG of the power transistor, thereby decreasing the charging and discharging time constant associated with the large gate parasitic capacitance and improving the gate speed of M_P. A quantitative analysis of the low-output-impedance characteristic of the LS FVF is presented below.

When a test voltage $v_t$ is applied to the gate node $V_{\mathrm{PG}}$ of the power transistor $M_P$, the small-signal voltage response $v_A$ at the internal node $V_A$ after signal amplification through $M_P$ and the common-gate transistor $M_1$ can be expressed as:

$$v_A=-g_{\mathrm{mP}}{R}_A{v}_t$$

(1)

Here, $g_{mP}$ denotes the transconductance of the power transistor M_P, and $R_A$ represents the equivalent impedance at node V_A, which can be approximated as $R_A={g_{\mathrm{mP}}r}_{oP}{r}_{o1}\parallel r_{\mathrm{oN}}$.

Based on Kirchhoff’s current law at the $V_{\mathrm{PG}}$ node, the approximate expression for the small-signal output impedance at $V_{\mathrm{PG}}$ can be derived as:

$$R_{\mathrm{out},\mathrm{VPG}}={\displaystyle \frac{v_t}{i_t}}={\displaystyle \frac{1}{g_{\mathrm{mLS}}{(g}_{\mathrm{mP}}{R}_A+1)}}.$$

(2)

Here, $g_{\mathrm{mLS}}$ denotes the transconductance of the level-shifting transistor $M_{\mathrm{LS}}$Since the transconductance of the power transistor $g_{\mathrm{mP}}$ is sufficiently large and satisfies $g_{\mathrm{mP}}{R}_A\gg 1$, the above expression can be further simplified for engineering analysis as:

$$R_{\mathrm{out},\mathrm{VPG}}\approx {\displaystyle \frac{1}{g_{\mathrm{mLS}}{g}_{\mathrm{mP}}{R}_A}}.$$

(3)

The charging and discharging time constant at node $V_{\mathrm{PG}}$ under LS FVF drive is reduced to:

$${\tau }_{\mathrm{LS}\mathrm{FVF}}=R_{\mathrm{out},\mathrm{VPG}}\cdot C_{G,\mathrm{MP}}\approx {\displaystyle \frac{C_{G,\mathrm{MP}}}{g_{\mathrm{mLS}}{g}_{\mathrm{mP}}{R}_A}}\ll {\tau }_{\mathrm{FVF}}\approx {\displaystyle \frac{C_{G,\mathrm{MP}}}{g_{m2}+g_{mP}}}.$$

(4)

Here, ${\tau }_{\mathrm{FVF}}$ denotes the time constant at $V_{\mathrm{PG}}$ in the conventional FVF shown in Figure 2, where the equivalent resistance at this node is approximately ${\displaystyle \frac{1}{g_{m2}+g_{\mathrm{mP}}}}$. In the proposed design, $g_{\mathrm{mLS}}{R}_A\gg 1$, resulting in an $R_{\mathrm{out},\mathrm{VPG}}$ that is significantly lower than the equivalent resistance at $V_{\mathrm{PG}}$ in the conventional FVF, thereby substantially reducing the associated time constant. Therefore, compared with the conventional FVF, the LS FVF further reduces the equivalent impedance at the gate node of the power transistor, shifting the corresponding pole toward higher frequencies and shortening the small-signal settling time. The large-signal slew rate is instead determined by the charging and discharging currents at the $V_{\mathrm{PG}}$ node.

2.2. Analysis and Design of the Capacitive-Coupled Dynamic Biasing Circuit (CCDB) and the Positive Feedback Auxiliary (PFA) Circuits

To address the trade-off between low quiescent current and fast transient response caused by the fixed current biasing in the LS FVF circuit, two auxiliary circuits, namely, a Capacitive-Coupled Dynamic Biasing (CCDB) and a Positive Feedback Auxiliary (PFA) circuit, are introduced to dynamically regulate the charging and discharging currents at $V_{\mathrm{PG}}$, thereby accelerating the transient response. When the load current increases abruptly and $V_{\mathrm{OUT}}$ decreases, the CCDB circuit raises $V_{\mathrm{BN}1}$, thereby increasing the current of $M_N$ and further enhancing the discharging current of $M_{\mathrm{LS}}$. As a result, the voltage at $V_{\mathrm{PG}}$ rapidly decreases, increasing the current through $M_P$ to compensate for the load variation and maintain a stable $V_{\mathrm{OUT}}$. To further accelerate the charging and discharging of the V_PG node, a PFA circuit is proposed, which dynamically adjusts the current of the charging current source $M_{\mathrm{LSP}}$ and introduces an additional discharge branch to adaptively regulate the discharge current at the $M_P$ node.

2.2.1. Capacitive-Coupled Dynamic Biasing Circuit

The CCDB circuit, highlighted in blue in Figure 5, employs capacitive coupling to sense variations in the output voltage and dynamically adjust the current of the current-source transistor $M_N$. Under steady-state conditions, capacitor $C_2$ behaves as an open circuit at dc. In this condition, $M_6$–$M_9$ together with resistor $R_2$ establish a stable dc bias, maintaining $V_{\mathrm{BN}1}$ at the desired level. Consequently, $M_N$ provides only the baseline tail current required for proper operation of the LS FVF. Therefore, under light-load or steady-output conditions, the fast loop does not continuously operate at a high bias current. When the load current increases abruptly, $V_{\mathrm{OUT}}$ undergoes a rapid undershoot. This voltage variation is coupled through $C_2$ to the gate of $M_6$. As $V_{\mathrm{OUT}}$ decreases, the gate voltage of $M_6$ also drops momentarily, enhancing the conduction of the PMOS transistor $M_6$ and thereby rapidly raising $V_{\mathrm{BN}1}$. The resulting increase in $V_{\mathrm{BN}1}$ increases the current through the LS FVF tail transistor $M_N$, thereby providing the fast loop with enhanced current-driving capability. Unlike a conventional approach that continuously increases the quiescent bias current, the proposed dynamic biasing technique temporarily enhances the transconductance and drives current of the critical branches only during output transients and restores the circuit to its low-power state once the transient subsides. In the design, the CCDB circuit draws a quiescent current of 15 μA under full-load conditions.

To quantitatively assess the transient-response enhancement achieved by the CCDB circuit, comparative simulations were conducted with the CCDB enabled and disabled, while all other conditions, including the pass-transistor dimensions, LS FVF fast loop, and slow main loop, were kept identical. With a 200-pF load capacitance, the load current was stepped between 0 and 400 mA with a 100-ns transition time, and the resulting transient responses are shown in Figure 6.

Without CCDB, the LDO output voltage drops to a minimum of approximately 1.08 V, corresponding to an undershoot of about 117.2 mV; with CCDB enabled, the minimum output voltage increases to approximately 1.15 V and the undershoot is reduced to about 45.6 mV. Meanwhile, a pronounced reverse overshoot occurs after the initial undershoot when CCDB is disabled, whereas this secondary voltage disturbance is significantly suppressed when CCDB is employed. This improvement arises because the output-voltage drop is coupled to the LS FVF tail-current control node through the CCDB, transiently increasing the effective transconductance of the fast loop and enhancing the gate-discharge capability, thereby allowing the power PMOS transistor to increase the output current more rapidly. When the current load transitions from heavy load to light load, the initial overshoot peaks are similar with and without CCDB, indicating that it does not provide a significant improvement for this transition.

2.2.2. Positive Feedback Auxiliary Circuit

The PFA circuit, highlighted in orange in Figure 5, dynamically regulates the charging and discharging currents of the $V_{\mathrm{PG}}$ node. Under steady-state conditions, the PFA provides the gate-bias voltage $V_{\mathrm{BP}3}$ for the current-source transistor $M_{\mathrm{LSP}}$ of the level shifter. When the load current increases abruptly, the LS FVF pulls $V_{\mathrm{PG}}$ downward, increasing $I_{M2}$ and consequently raising $V_{\mathrm{BP}3}$, which reduces the charging current supplied by $M_{\mathrm{LSP}}$ to $V_{\mathrm{PG}}$ and thereby accelerates its voltage drop. To further accelerate the voltage drop at this node, a current mirror formed by $M_3$ and $M_4$ provides an additional discharge path for $V_{\mathrm{PG}}$. Therefore, the PFA circuit adaptively regulates the charging and discharging currents of $V_{\mathrm{PG}}$, further improving the response speed of the LS FVF. The PFA circuit draws a quiescent current of approximately 200 μA under full-load conditions.

To further verify the improvement in transient performance provided by the PFA circuit, comparative load-transient simulations were performed with and without the PFA circuit. Under identical simulation conditions, the load current was switched between 0 and 400 mA with a transition time of 100 ns, while the output load capacitance was maintained at 200 pF. As shown in Figure 7, without the PFA circuit, the limited charging and discharging capability of the LS FVF fast loop at the power-transistor gate node $V_{\mathrm{PG}}$ results in a relatively large output-voltage deviation during load transients, with a maximum deviation of approximately 68.9 mV. In contrast, with the PFA circuit enabled, the maximum output-voltage deviation is reduced to approximately 45.6 mV, resulting in a significant improvement in transient performance. This improvement is primarily attributed to the PFA circuit dynamically regulating the charging and discharging of the $V_{\mathrm{PG}}$ node.

2.3. Analysis and Design of an RFC-Based EA

In the proposed dual-loop LDO architecture, the slow main loop is primarily responsible for high-accuracy DC regulation and steady-state output-voltage control. As the core building block of the slow main loop, the gain and bandwidth of the EA are key factors determining the LDO’s line regulation, load regulation, and low-frequency PSRR. To enhance both gain and bandwidth without increasing the quiescent power consumption, an EA based on the Recycling Folded-Cascode (RFC) topology is adopted in the design.

Although the conventional Folded-Cascode (FC) amplifier provides a wide input common-mode range and high output resistance, its folded branches are primarily used for DC biasing and small-signal current transfer rather than directly contributing to transconductance amplification, resulting in limited transconductance efficiency per unit bias current. The RFC topology reuses the bias-branch currents of the conventional folded-cascode amplifier, allowing currents that would otherwise contribute only marginally to signal amplification to be converted into effective transconductance, thereby improving the transconductance, unity-gain bandwidth, and slew rate at approximately the same power consumption [24,25,26,27]. As illustrated by the RFC block in Figure 8, the input differential pair is proportionally split, and a cross-coupled current-mirror ratio K is employed to constructively combine the small-signal currents in the folded branches with the input-signal current, thereby substantially enhancing the effective transconductance without increasing the tail bias current. The low-frequency voltage gain of the RFC amplifier, $A_{V,\mathrm{RFC}}$, can be expressed as:

$$A_{V,\mathrm{RFC}}\approx -\left(1+K\right)g_{m18}\left\{\left[g_{m30}{r}_{o30}{r}_{o28}\right]\parallel \left[g_{m32}{r}_{o32}\left(r_{o18}\parallel r_{o26}\right)\right]\right\}.$$

(5)

$g_{\mathrm{mi}}$ and $r_{\mathrm{oi}}$ denote the transconductance and small-signal output resistance, respectively, of transistor $M_i$ in Figure 8, while K represents the current-mirror ratio of the RFC cross-coupled current mirror and is set to 3 in the design.

As shown in Figure 9, the simulated RFC EA achieves a DC gain of approximately 70 dB and a unity-gain bandwidth of 50 MHz while drawing only approximately 65 μA. The high DC gain effectively suppresses the impact of supply disturbances and load-current variations on the output voltage, thereby improving both line and load regulation.

3. Loop Stability and Frequency Compensation Design

The complete circuit of the proposed LDO is shown in Figure 10. Due to the presence of two loops and multiple amplification stages, frequency compensation is required to ensure stable operation. In the design, the load current varies from 0 to 400 mA, causing the pole locations associated with the power transistor $M_P$ to shift by several orders of magnitude due to the variations in its transconductance $g_{\mathrm{mP}}$ and output resistance $R_{\mathrm{OUT}}$, which poses a significant challenge to system stability. In this section, the loop is broken at the output node $V_{\mathrm{OUT}}$ to establish the small-signal model of the open-loop system, derive its transfer function, and analyze the frequency compensation mechanism, as illustrated in Figure 11.

Neglecting the poles located well beyond the unity-gain bandwidth, four dominant nodes need to be considered: the EA output node $V_{\mathrm{CTRL}}$, the LS FVF internal node $V_A$, the power-transistor gate node $V_{\mathrm{PG}}$, and the output node $V_{\mathrm{OUT}}$. Therefore, with the PFA circuit retained while temporarily neglecting the frequency-compensation networks formed by $R_C-C_C$ and $C_1-R_1$, the uncompensated open-loop gain $T_0\left(s\right)$ can be approximated as:

$$T_0\left(s\right)\approx {\displaystyle \frac{-A_0}{\left(1+\frac{s}{{\omega }_{p,\mathrm{CTRL}}}\right)\left(1+\frac{s}{{\omega }_{p,A}}\right)\left(1+\frac{s}{{\omega }_{p,\mathrm{PG}}}\right)\left(1+\frac{s}{{\omega }_{p,\mathrm{OUT}}}\right)}}.$$

(6)

Here, $A_0$ denotes the magnitude of the equivalent DC loop gain., while ${\omega }_{p,\mathrm{CTRL}}$, ${\omega }_{p,A}$, ${\omega }_{p,\mathrm{PG}}$, and ${\omega }_{p,\mathrm{OUT}}$ represent the four poles considered in the small-signal model, respectively.

The RFC EA output node $V_{\mathrm{CTRL}}$ exhibits a high output resistance $R_{\mathrm{EA}}$, with its equivalent node capacitance denoted as $C_{\mathrm{EA}}$. Therefore, without the dynamic compensation branch, the absolute value of the corresponding pole can be approximately expressed as ${\omega }_{p,\mathrm{CTRL}}\approx {\displaystyle \frac{1}{R_{\mathrm{EA}}{C}_{\mathrm{EA}}}}$. In the design, the RFC EA exhibits a high output impedance and relatively large parasitic capacitance, making $V_{\mathrm{CTRL}}$ the dominant pole of the system. The primary objective of the subsequent compensation scheme is not to alter this low-frequency dominant pole, but rather to control the non-dominant poles that follow and mitigate the additional phase shift introduced by these poles.

The second node that requires consideration is $V_A$, which is located within the fast path of the LS FVF. If $R_A$ and $C_A$ denote the equivalent small-signal resistance and total parasitic capacitance at this node, respectively, the absolute value of the corresponding pole without compensation can be approximated as ${\omega }_{p,A}\approx {\displaystyle \frac{1}{R_A{C}_A}}$. Since $V_A$ is located inside the LS FVF fast loop, its pole directly affects the phase shift of the fast path in the medium- and high-frequency regions. When ${\omega }_{p,A}$ approaches the unity-gain frequency of the loop, the additional phase lag introduced by this pole combines with those from the other two non-dominant poles, becoming one of the major stability limitations in high-bandwidth designs.

The third critical pole is located at the $V_{\mathrm{PG}}$ node. To support a maximum load current of 400 mA, the power transistor $M_P$ requires a large device size, resulting in a substantial parasitic gate capacitance $C_{G,\mathrm{MP}}$ at this node. Accordingly, the absolute value of the pole at $V_{\mathrm{PG}}$ can be approximated as:

$${\omega }_{p,\mathrm{PG}}\approx {\displaystyle \frac{g_{\mathrm{mLS}}{g}_{\mathrm{mP}}{R}_A}{C_{G,\mathrm{MP}}}}.$$

(7)

The fourth critical pole is located at the output node $V_{\mathrm{OUT}}$. When $C_L$ is much larger than the parasitic capacitance at the output node, the absolute value of the output pole can be approximated as ${\omega }_{p,\mathrm{OUT}}\approx {\displaystyle \frac{1}{R_{\mathrm{OUT}}{C}_L}}$. Here, $R_{\mathrm{OUT}}$ denotes the small-signal equivalent resistance at the output node, and $C_L$ is the load capacitance. Unlike the poles associated with the three internal nodes, ${\omega }_{p,\mathrm{OUT}}$ is highly sensitive to the load current. At light loads, the transconductance of the power transistor decreases while the equivalent output resistance increases, causing the output pole to shift toward lower frequencies and potentially approach the internal non-dominant poles, such that multiple poles may simultaneously fall within the unity-gain bandwidth and significantly degrade system stability. Under heavy-load conditions, the output pole shifts toward higher frequencies, while the power-transistor gate node $V_{\mathrm{PG}}$ and the internal node $V_A$ in the fast loop become the primary limitations on stability in the medium- and high-frequency regions.

Therefore, the proposed system does not exhibit a fixed arrangement of non-dominant poles over the entire load range. Instead, it behaves as four poles coupled system whose pole locations vary with the load condition. This load-dependent pole migration is also one of the primary reasons why a fixed single-zero compensation scheme is insufficient to ensure stability over the entire load range.

To increase the separation among the four poles, a Miller compensation branch composed of the series-connected $R_C$ and $C_C$ is first introduced between $V_A$ and $V_{\mathrm{OUT}}$. Assuming that the equivalent gain from $V_A$ to $V_{\mathrm{OUT}}$ is ${\displaystyle \frac{v_{\mathrm{out}}}{v_A}}\approx -A_F$, where $A_F>0$, the effective capacitance contributed by the Miller capacitor at $V_A$ can be approximated as $C_{A,\mathrm{eff}}\approx C_A+\left(1+A_F\right)C_C$, shifting the absolute value of the compensated pole at this node to:

$${\omega }_{p,A}^{\hspace{0.17em}’}\approx {\displaystyle \frac{1}{R_A\left[C_A+\left(1+A_F\right)C_C\right]}}.$$

(8)

Owing to the Miller multiplication of $C_C$ by the forward gain, the pole at $V_A$ is significantly separated from the subsequent high-frequency poles, thereby producing the well-known pole-splitting effect. In the proposed design, this compensation network is not intended to replace the low-frequency dominant pole at $V_{\mathrm{CTRL}}$. Instead, it establishes a controlled frequency separation within the fast LS FVF path, thereby preventing the phase contributions of $V_A$, $V_{\mathrm{PG}}$, and $V_{\mathrm{OUT}}$ from accumulating within the same frequency range around the unity-gain frequency.

Using the compensation capacitor alone introduces a right-half-plane zero through the feedforward current path. Therefore, a series resistor $R_C$ is employed to control the location of this zero and improve system stability. Denoting the equivalent transconductance of the downstream stages from $V_A$ to the output as $G_{\mathrm{mF}}$, the zero location under the conventional first-order Miller compensation approximation can be expressed as:

$${\omega }_{z,C}\approx {\displaystyle \frac{1}{C_C\left(\frac{1}{G_{\mathrm{mF}}}-R_C\right)}}.$$

(9)

When $R_C={\displaystyle \frac{1}{G_{\mathrm{mF}}}}$, the zero introduced by the feedforward path through the compensation capacitor is pushed to a very high frequency. By further setting $R_C>{\displaystyle \frac{1}{G_{\mathrm{mF}}}}$, the zero is shifted into the left-half plane, providing positive phase lead in the mid-frequency region. In the design, $R_C$ and $C_C$ are set to 300 Ω and 29 pF, respectively. $R_C$ remains greater than ${\displaystyle \frac{1}{G_{\mathrm{mF}}}}$ over the entire load range, thereby improving system stability.

For large load-current variations, the fixed $R_C-C_C$ compensation network alone is insufficient to ensure system stability over the entire load range. To address this issue, a dynamic pole-zero compensation network composed of $C_1$ and MOS transistor $M_{33}$ is further introduced at the $V_{\mathrm{CTRL}}$ node. Unlike a fixed resistor, the equivalent resistance of $M_{33}$, denoted as $R_1$, varies with $V_{\mathrm{CTRL}}$. In the design, $R_1$ is approximately 30 Ω under no-load conditions, and $C_1$ is $20\mathrm{pF}$. The admittance at this node can be expressed as:

$$Y_{\mathrm{CTRL}}\left(s\right)={\displaystyle \frac{1}{R_{\mathrm{EA}}}}+s{C}_{\mathrm{EA}}+{\displaystyle \frac{s{C}_1}{1+s{R}_1{C}_1}}.$$

(10)

Accordingly, the corresponding impedance can be expressed as:

$$Z_{\mathrm{CTRL}}\left(s\right)={\displaystyle \frac{R_{\mathrm{EA}}\left(1+s{R}_1{C}_1\right)}{1+s\left[R_1{C}_1+R_{\mathrm{EA}}\left(C_{\mathrm{EA}}+C_1\right)\right]+s^2{R}_{\mathrm{EA}}{R}_1{C}_{\mathrm{EA}}{C}_1}}.$$

(11)

As indicated by (11), the introduction of the $C_1-R_1$ network introduces an additional zero located at ${\omega }_{z,1}=-{\displaystyle \frac{1}{R_1{C}_1}}$. Since $R_{\mathrm{EA}}\gg R_1$ in the design, the two poles can be approximately expressed as:

$${\omega }_{p,L}\approx -{\displaystyle \frac{1}{R_{\mathrm{EA}}\left(C_{\mathrm{EA}}+C_1\right)}},$$

(12)

and

$${\omega }_{p,H}\approx -{\displaystyle \frac{C_{\mathrm{EA}}+C_1}{R_1{C}_{\mathrm{EA}}{C}_1}}.$$

(13)

Therefore, the resulting pole-zero locations approximately satisfy the frequency relationship ${|\omega }_{p,L}|<{|\omega }_{z,1}|<|{\omega }_{p,H}|$.

In the low-frequency region, $C_1$ behaves approximately as an open circuit, allowing the RFC to retain a high output impedance and DC gain without significantly affecting the steady-state regulation of the main loop. In the mid-frequency region, the zero ${\omega }_{z,1}$ provides phase lead to compensate for the phase lag introduced by the poles at $V_A$, $V_{\mathrm{PG}}$, and the LDO output, while its location adaptively shifts with the output pole. At higher frequencies, ${\omega }_{p,H}$ shifts dynamically relative to the output pole to maintain system stability. At light loads, the output pole moves toward the origin. Meanwhile, the EA output voltage decreases, increasing $R_1$ and consequently shifting the introduced zero ${\omega }_{z,1}$ toward the origin, thereby maintaining sufficient phase margin. Therefore, compared with conventional fixed-zero compensation, the proposed network preserves high low-frequency gain while selectively providing phase boost in the mid-frequency region, where the system stability is most critical.

Based on the above analysis, the compensated loop transfer function can be expressed as:

$$T\left(s\right)\approx {\displaystyle \frac{A_0\left(1+\frac{s}{{\omega }_{z,C}}\right)\left(1+\frac{s}{{\omega }_{z,1}}\right)}{\left(1+\frac{s}{{\omega }_{p,L}}\right)\left(1+\frac{s}{{\omega }_{p,H}}\right)\left(1+\frac{s}{{\omega }_{p,A}^{\text{‘}}}\right)\left(1+\frac{s}{{\omega }_{p,\mathrm{PG}}}\right)\left(1+\frac{s}{{\omega }_{p,\mathrm{OUT}}}\right)}}.$$

(14)

System stability is ensured by three coordinated frequency-compensation mechanisms. First, the low output impedance of the LS FVF pushes the gate pole ${\omega }_{p,\mathrm{PG}}$ of the large pass transistor to high frequencies. Second, the $R_C-C_C$ network provides pole splitting and controls the Miller zero along the fast $V_A-V_{\mathrm{OUT}}$ path. Finally, the $C_1-R_1$ network introduces adaptive pole-zero compensation that tracks the output pole and provides additional phase lead in the mid-frequency region. Together, these mechanisms prevent multiple non-dominant poles from clustering near the unity-gain frequency. Simulation results show that, with C_L = 200 pF, the system maintains sufficient stability margins over the entire load-current range of 0–400 mA. As shown in Figure 12, the simulated phase margins at the TT process corner are approximately 46.7° at no load and 76.4° at full load. As shown in Figure 13, the no-load phase margins remain above 45° at both the SS and FF process corners, demonstrating the robustness of the proposed compensation scheme across process corners and over the full load range.

4. Layout Design and Post-Layout Simulation

4.1. Overall Circuit Layout Design

To verify the feasibility of the proposed LDO, the complete layout was implemented, as shown in Figure 14. The LDO core occupies approximately $173\mathsf{\mu }m\times 480\mathsf{\mu }m$, while the overall layout including the I/O pads measures $460\mathsf{\mu }m\times 620\mathsf{\mu }m$. In the layout, the power transistor adopts a multi-finger structure and multilayer metal routing to reduce parasitic resistance and improve current-distribution uniformity. Meanwhile, the critical analog blocks are appropriately isolated from the high-current power paths to mitigate the impact of substrate noise and supply disturbances induced by large current variations through the power transistor of the EA and feedback nodes. In addition, matching-sensitive devices, such as the differential input pair and current mirrors, are designed using common-centroid and symmetric techniques to minimize mismatch caused by process variations. The final layout includes I/O pads, providing the implementation required for subsequent parasitic extraction and post-layout simulations.

4.2. LDO Post-Layout Simulation Results

To evaluate the performance of the proposed LDO, post-layout simulations were performed after layout implementation, including evaluations of the transient response, line regulation, load regulation, PSRR, and so on.

In the post-layout simulations, the load capacitance was set to 200 pF, and the load current was stepped between 0 and 400 mA with a transition time of 100 ns. The transient responses of the LDO at different process corners are shown in Figure 15. The results are summarized in Table 1, the proposed LDO exhibits recovery times of no more than 0.2 μs and small output-voltage excursions, demonstrating the effectiveness of the proposed design. The recovery time is defined as the interval from the load-step edge until the output voltage re-enters and subsequently remains within ±1% of its steady state value.

The post-layout simulation results for line regulation are shown in Figure 16. At the full-load current of 400 mA, the proposed LDO achieves line-regulation values of 2.1 mV/V, 1.1 mV/V, and 2.8 mV/V at the TT, FF, and SS process corners, respectively.

The post-layout simulation results for load regulation are shown in Figure 17, where the load current $I_{\mathrm{LOAD}}$ is continuously swept from 0 to 400 mA. At a current load of 400 mA, the DC output voltage at the TT process corner decreases by approximately 9.72 mV from its no-load value, corresponding to a load regulation of approximately 24.3 μV/mA. An approximately linear decrease in the output voltage is also observed at the other corners, with load-regulation values of 24.4 μV/mA and 24.5 μV/mA at the SS and FF corners, respectively.

The post-layout simulation results for the PSRR at a current load of 400 mA are shown in Figure 18. At the TT process corner, the low-frequency PSRR reaches -50 dB. As the frequency increases beyond the dominant-pole frequency, the open-loop gain of the EA begins to roll off, gradually weakening the noise-rejection capability of the main loop. Nevertheless, the PSRR remains approximately -20 dB at 100 kHz. Although slight differences in low-frequency PSRR are observed among the SS, TT, and FF process corners, their overall frequency responses remain highly consistent.

4.3. Performance Comparison

Table 2 compares the performance of the proposed LDO with that of recently reported FVF-based LDOs. Since these designs differ in process technology, operating voltage, load-current range, load capacitance, and other conditions, the reported metrics are intended only as an overall performance reference. Implemented in a 130-nm CMOS process, the proposed LDO supports the maximum load current of 400 mA and achieves a current efficiency of 99.78%. Under a 0–400 mA load step with a 200-pF load capacitance, the proposed LDO exhibits a maximum output-voltage deviation of 100.4 mV and a recovery time of 200 ns at the TT process corner, while achieving an FOM_C of only 0.113 ps. Compared with prior works, the relatively low FOM_C indicates that the proposed design achieves a favorable trade-off among load-current range, transient performance, and quiescent power consumption.

The capacitance-normalized transient figure of merit, FOM_C [31], adopted in Table 2 is defined as:

$$\mathrm{FO}{M}_C={\displaystyle \frac{C_L\mathsf{\Delta }{V}_{\mathrm{OUT}}{I}_Q}{{\left(\mathsf{\Delta }{I}_{\mathrm{LOAD}}\right)}^2}}.$$

(15)

Here, C_L denotes the output load capacitance, $\mathsf{\Delta }{V}_{\mathrm{OUT}}$ is the maximum transient deviation of the output voltage from its steady-state value during a load-current step, taken as the larger magnitude of the overshoot and undershoot, $I_Q$ is the quiescent current of the LDO, and $\mathsf{\Delta }{I}_{\mathrm{LOAD}}$ represents the magnitude of the load-current step.

5. Conclusions

Targeting the digital power-supply requirements of X-ray detector readout ASICs, this work presents an improved LS FVF-based LDO implemented in a 130-nm CMOS process. To improve the transient response, an FVF-based fast loop is introduced in addition to the conventional main regulation loop. To alleviate the mutual constraint on the DC operating points imposed by the shared node in a conventional FVF, a level shifter is introduced to form the LS FVF. However, the fixed biasing of the LS FVF limits the transient response speed of the LDO under large load-current variations. To address this limitation, the CCDB and the PFA circuits are proposed to accelerate the charging and discharging of the pass-transistor gate. In addition, to ensure system stability over a wide load-current range, a dynamic pole-zero tracking compensation scheme is introduced in conjunction with Miller compensation.

Post-layout simulation results demonstrate that the proposed LDO achieves fast transient response and robust stability over a load current range of 0–400 mA and across different process corners, validating the effectiveness of the proposed CCDB, PFA, and frequency-compensation circuits. Moreover, the LDO achieves an FOM_C of only 0.113 ps, indicating a favorable tradeoff among load current range, transient performance, and quiescent power consumption, making it well suited for X-ray detector readout chips and other on-chip power-supply applications subject to large and rapid load-current variations.