From Predict to Generate: A Cross-Layer Survey of Generative AI for IC Design and Manufacturing

1. Introduction

Chip design is under strain. Designs are larger, rules are tighter, and time-to-market is unforgiving. First-time-right tape-outs are slipping, and verification loads keep rising [1,2]. Machine learning (ML) has emerged as a key tool for addressing these pressures, with demonstrated gains across the EDA stack in areas ranging from logic synthesis and placement to analog sizing and reliability analysis. This paper critically reviews the application of generative AI to chip design, covering work in analog/mixed-signal (AMS) design, logic design, physical design, and manufacturing reliability, and examines how these methods are evaluated and what gaps remain.

Prior literature reviews have been focused rather than comprehensive. Broad ML-in-EDA surveys document general progress but do not treat generative methods as a primary lens [3,4]. Focused reviews of ML for routing [5] and placement [6] cover those subproblems in depth but do not connect them to upstream design or downstream manufacturability. Surveys of AMS design tools emphasize sizing and modeling but predate or only briefly touch LLM- and agent-based generators [7,8]. Reviews of analog layout tools detail ML-assisted placement and routing but do not address multi-agent LLM workflows or knowledge-graph retrieval [9]. For digital layout generation, deep-learning overviews center on discriminative predictors rather than modern generative loops [10]. Generative surrogates and physics-integrated models are starting to be used for manufacturing analysis including hotspot correction, mask optimization, and reliability prediction—but those recent developments are not included in prior surveys [7,8,10]. In manufacturing, surveys of ML for semiconductor process optimization [11] and anomaly detection [12] synthesize broad methods, and computational lithography now has community datasets [13], yet a unifying account of generative models across defect modeling, mask optimization, and hotspot correction—and how they connect to earlier design stages—is missing. Recent surveys on LLMs for EDA [14] and circuit foundation models [15] address the rise of large pretrained models but do not span all layers of the design flow or tie coverage to datasets, evaluation practice, and reproducibility.

This review addresses that gap. We survey generative AI methods across all layers of the IC design flow, organizing the field by what is generated (circuits, code/flows, layouts, masks, surrogates) and how generation is grounded (retrieval/KG, simulators, and physics). We connect AMS, logic, physical design, and yield/reliability, and we highlight where generation must close the loop with analysis and verification. We also surface practical issues such as data curation, benchmarks, and reproducibility that limit deployment in industrial flows.

We claim the following contributions:

• A unified taxonomy for generative EDA. We classify model families—LLM agents, graph/sequence generators, diffusion and GAN pipelines, and physics-integrated autoencoders—by their artifacts and feedback signals. This complements LLM-specific and foundation-model surveys by placing them in a full-flow context [14,15].
• Cross-stage integration. We map how analog and digital netlists propagate into physical design, and illustrate the bidirectional interplay where EM/stress budget and DFM feedback from the manufacturing stage inform and refine earlier synthesis and layout decisions. Prior reviews treat these areas in isolation; we connect them with concrete interfaces and failure modes [10,13].
• Evidence and evaluation. We summarize representative datasets, benchmarks (e.g., LithoBench for computational lithography [13]), and recurring evaluation gaps, especially where cross-paper comparison is weak.
• Data bottlenecks by stage. We distinguish between corpus scarcity, label scarcity, proprietary tool-output dependence, and benchmark fragmentation, and show how each bottleneck shapes which generative methods are practical in logic, AMS, physical design, and manufacturing.
• Guidance for practitioners. We outline when to favor retrieval-grounded LLM agents versus task-specific generators, where physics priors are essential. We discuss practical data-availability constraints and their implications for model choice. We relate these choices to compute limits and toolchain realities [14].

Scope. We cover (i) AMS topology, sizing, layout, and document-to-netlist extraction; (ii) logic synthesis and flow orchestration; (iii) physical-design scripting, placement, and routability-aware generation; and (iv) manufacturing, yield, and reliability, including hotspot correction, mask optimization, and defect modeling. We emphasize recent work, while retaining influential earlier generative systems where they remain foundational. Representative prior surveys we build upon include Pan et al. on LLMs for EDA [14], Fang and Xie et al. on circuit foundation models [15], Shi et al. on intelligent layout generation [10], and Mina et al. and Martins on AMS design automation [7,8].

Why now? Design teams face mounting complexity while tool behavior grows harder to tune by hand. Generative methods can search design spaces that heuristics skip and can tie design choices to downstream manufacturing constraints. In recent years, we have seen increasingly generative applications in IC related paper (Figure 1). Without a cross-layer view, however, teams risk optimizing locally in ways that create problems later in the flow. This survey highlights representative examples and recurring risks [1,2].

Organization. Figure 2 maps the silicon design cycle as a connected system consisting of four main components. Analog IC design and logic synthesis provide the foundational netlists and constraints that dictate the requirements for physical design. This implementation phase yields the GDSII and masks necessary for IC manufacturing and lithography. The framework incorporates feedback loops for reliability corners and DFM/hotspot data, ensuring that downstream manufacturing realities refine upstream design choices and turning a linear sequence into an iterative, cross-layer workflow.

The remainder of this article follows the stages of this integrated flow. Section II establishes the taxonomy of generative models and grounding strategies. Section III treats digital logic synthesis and flow optimization. Section IV surveys analog design, from topology synthesis to netlist extraction. Section V covers physical design, focusing on script generation and placement. Section VI examines manufacturing, yield, and reliability, including computational lithography and physics-aware surrogates. Section VII concludes the article.

2. Background on Generative AI

Generative models aim to approximate the underlying probability distribution $p_{\mathrm{data}}\left(\mathbf{x}\right)$ of observed data, where $\mathbf{x}$ denotes a data sample, and to synthesize new samples $\tilde{\mathbf{x}}\sim p_{\theta }\left(\mathbf{x}\right)$ that preserve the statistical characteristics of the original dataset, where $\theta$ denotes the learned model parameters. Over the past decade, their architectures have evolved from latent-representation reconstruction to attention-driven reasoning capable of processing multimodal data, as shown in Figure 3. This section provides an overview of the four generative model families that underlie recent developments in EDA: autoencoder-based models [16], generative adversarial networks (GANs) [17], diffusion models [18], and transformer-based models [19] (including large language models, LLMs). The subsection headers list the year in which each model family was first introduced in the machine learning literature; EDA applications followed in subsequent years.

2.1. Autoencoder-Based Models (2013– )

Autoencoders learn a low-dimensional representation $\mathbf{z}$ by jointly training an encoder $E_{\varphi }$, parameterized by $\varphi$, and a decoder $D_{\theta }$, parameterized by $\theta$:

$$\mathbf{z}=E_{\varphi }\left(\mathbf{x}\right),\widehat{\mathbf{x}}=D_{\theta }\left(\mathbf{z}\right),$$

with a reconstruction loss such as $\parallel \mathbf{x}-\widehat{\mathbf{x}}{\parallel }_2^2$. The variational autoencoder (VAE) formulates this in a probabilistic framework and optimizes the evidence lower bound (ELBO) [16]:

$${\mathcal{L}}_{\mathrm{VAE}}={\mathbb{E}}_{q_{\varphi }\left(\mathbf{z}\right|\mathbf{x})}\left[-log{p}_{\theta }\left(\mathbf{x}\right|\mathbf{z})\right]+\mathrm{KL}\left(q_{\varphi }\left(\mathbf{z}\right|\mathbf{x})\parallel p\left(\mathbf{z}\right)\right),$$

where the Kullback-Leibler term regularizes the latent space toward a simple prior $p\left(\mathbf{z}\right)=\mathcal{N}(0,\mathbf{I})$. Variants such as physics-integrated autoencoders [20] further enhance robustness and interpretability by embedding domain constraints into the learned representations.

In EDA, autoencoder-based models have been applied to several tasks. They learn compact latent representations of chip-level power and thermal maps to accelerate sign-off analysis [21,22,23]. They also enable inverse design of device and process parameters through exploration of the latent space [24]. In addition, physics relationships can be embedded directly into the decoder so that generated outputs respect known physical laws, producing reliable surrogates for manufacturing and design optimization [20,24].

2.2. Generative Adversarial Networks (2014– )

Generative adversarial networks (GANs) [17] introduce an adversarial optimization between a generator $G_{\theta }$ and a discriminator $D_{\varphi }$:

$$\underset{\theta }{min}\underset{\varphi }{max}\left[{\mathbb{E}}_{\mathbf{x}\sim p_{\mathrm{data}}}log{D}_{\varphi }\left(\mathbf{x}\right)+{\mathbb{E}}_{\mathbf{z}\sim p\left(\mathbf{z}\right)}log\left(1-D_{\varphi }\left(G_{\theta }\left(\mathbf{z}\right)\right)\right)\right].$$

The generator $G_{\theta }$ maps a noise vector $\mathbf{z}$ to a synthetic sample, while the discriminator $D_{\varphi }$ learns to distinguish real from generated samples. Two widely used variants are relevant to EDA applications. In the conditional GAN (cGAN), auxiliary information $\mathbf{y}$ (e.g., process conditions or design constraints) is incorporated to model $p\left(\mathbf{x}\right|\mathbf{y})$, enabling targeted generation for specific design scenarios. The Wasserstein GAN (WGAN) replaces the Jensen-Shannon divergence with the Earth-Mover distance to improve training stability, which is important when training data are scarce or imbalanced, as is common in EDA [17].

GANs are generally more expressive than autoencoders and tend to produce sharper, more realistic outputs because the adversarial discriminator penalizes blurry or averaged generations that reconstruction-based losses permit [17]. In EDA, GANs have been used to model hotspot distributions for lithography analysis [21], to learn failure distributions for reliability modeling [25], to augment datasets for rare-event learning [26,27], and to generate layouts and routing solutions conditioned on timing, power, and area constraints [28,29,30]. Conditional generation enables what-if exploration in early design stages and increases data diversity for downstream learning tasks.

2.3. Diffusion Models (2020– )

Diffusion models learn to reverse a gradual noising process. The forward process adds Gaussian noise over T steps, producing a sequence of increasingly noisy versions of a data sample ${\mathbf{x}}_0$. At each step t, the noisy sample ${\mathbf{x}}_t$ is obtained from the previous step via:

$$q\left({\mathbf{x}}_t\right|{\mathbf{x}}_{t-1})=\mathcal{N}\left(\sqrt{1-{\beta }_t}{\mathbf{x}}_{t-1},{\beta }_t\mathbf{I}\right),$$

where ${\beta }_t$ is a variance schedule coefficient that controls how much noise is added at step t. A neural network ${ϵ}_{\theta }$ is trained to predict and remove the noise:

$${\mathcal{L}}_{\mathrm{diff}}={\mathbb{E}}_{t,{\mathbf{x}}_0,ϵ}\left[\parallel ϵ-{ϵ}_{\theta }({\mathbf{x}}_t,t){\parallel }_2^2\right].$$

New samples are generated by starting from pure noise and iteratively applying the learned denoising network, yielding stable and diverse outputs [18]. Extensions such as conditional diffusion, latent diffusion, and classifier-guided diffusion allow generation to be steered toward desired properties.

Because the forward and reverse processes operate on fixed-size inputs, diffusion models are naturally suited to image-like data, and most EDA applications treat layout patterns, lithographic contours, or defect maps as images. In EDA, diffusion models have been applied to layout pattern completion, where a partial routing is extended to a complete solution [10]; to the synthesis of realistic defect images, which augments inspection datasets that are otherwise limited by the rarity of real defects [31]; and to the generation of design-rule-compliant layout patterns for design-for-manufacturability (DFM) analysis [32]. Diffusion models have also been used to emulate process variation and device degradation, providing a way to model physical uncertainties without running full physics-based simulations.

2.4. Transformer-Based Models (2017– )

The Transformer architecture captures long-range dependencies through a self-attention mechanism [19]:

$$\mathrm{Attention}(Q,K,V)=\mathrm{softmax}\left({\displaystyle \frac{Q{K}^{\top }}{\sqrt{d_k}}}\right)V,$$

where Q, K, and V are query, key, and value matrices formed by learned linear projections of input tokens, and $d_k$ is the dimension of the key vectors. Under the autoregressive objective

$${\mathcal{L}}_{\mathrm{Transf}}=-\sum _{t}log{p}_{\theta }\left(x_t\right|x_{<t}),$$

the model learns to predict each token given all preceding tokens, capturing the joint distribution of sequential or graph-structured data. Large language models (LLMs) are transformers trained on large text and code corpora, which gives them broad language understanding, reasoning capability, and the ability to generate and interpret structured formats such as netlists and EDA tool scripts.

Transformer models are currently considered state-of-the-art among generative architectures, though their large parameter counts require correspondingly large training datasets. In EDA, transformers and LLMs have been applied to analog circuit topology selection and sizing [33,34,35], as well as to design rule synthesis and EDA script generation [36,37]. Their attention mechanism captures hierarchical dependencies among circuit components and design constraints, while the broader language understanding of LLMs enables conversational interfaces, automatic code generation, and cross-tool reasoning.

2.5. Taxonomy of Generative Methods and Data Constraints

To place those model families in the context of the IC design cycle, Table 1 classifies specific generative tools and methods across logic synthesis, AMS design, physical design, and manufacturing. Each entry is characterized by its generation target (what the model produces), its grounding methodology (how generation is constrained or informed), and the feedback signal used to evaluate or refine the output.

While Table 1 organizes generative methods by their outputs, grounding mechanisms, and feedback signals, an equally important dimension is the availability and structure of data that support those methods. In practice, the feasibility of different generative approaches is often constrained not by model architecture, but by the type and quality of data available at each stage of the design flow. In Table 2, we summarized data limitations in generative EDA into four recurring categories: corpus scarcity, label scarcity, proprietary tool-output dependence, and benchmark fragmentation. Those bottlenecks manifest differently across domains. In logic synthesis, the main issue is the limited availability of broad, clean RTL corpora with reliable functional supervision. In AMS, the bottleneck is structured topology and simulation data, which are expensive to curate and often tied to expert design knowledge. In physical design, large datasets exist in principle, but many are locked behind proprietary tools, flows, and rule decks, limiting reproducibility. In manufacturing and reliability, the challenge is often not corpus size but label imbalance and restricted access to rare failure cases.

Those differences are not merely descriptive; they directly determine which generative strategies are practical in each domain. Foundation-style scaling is more viable where corpora are abundant, while retrieval, simulation feedback, and domain-specific models become more effective when data are sparse, structured, or confidential.

With growing interest in applying ML models to IC design in recent years, we have observed an increasing number of dataset-focused papers [38,39,40] aimed at benchmarking ML performance in this space. Adopting one or more of these datasets as standardized baselines can benefit the community by providing a common basis for comparison across different ML approaches.

In the following sections, we revisit each stage of the design flow—logic synthesis (Section III), AMS design (Section IV), physical design (Section V), and manufacturing and reliability (Section VI)—highlighting how data constraints shape both model design and evaluation practice.

Table 1. Summary of generative AI tools and methods organized by design stage.

Design Stage and Task	Method / Tool	Model and Grounding	Feedback / Signal
Logic Synthesis: RTL Generation and Circuit Construction	ChipChat [41]	LLM + interactive prompting	Verilog code, simulation logs
	DAVE / RTLcoder [42,43]	Fine-tuned LLM	Syntax checks, testbenches
	ShortCircuit [44]	Transformer + MCTS	AIG structure, Boolean equivalence
	T-Net [45]	Triangular network (Shannon decomp.)	Truth tables, logic correctness
	GPT-LS [46]	Decision transformer (offline RL)	Synthesis recipes, QoR metrics
	AISYN [47]	RL-based cut selection	AIG rewriting, area/power
	SOformer [48]	Causal transformer	QoR prediction, trajectory pruning
	Vaegan [26]	VAE-GAN hybrid	Synthetic HLS data, MMD
AMS Design: Topology Selection	AMSnet-KG [49]	LLM + KG-RAG retrieval	Simulation-driven sizing (BO)
	ADO-LLM [33]	LLM-guided Bayesian optimization	Sampling efficiency, FoM
	AnalogCoder [50,51]	LLM and MLLM	SPICE simulation, BO, functionality checks
	LaMAGIC [35]	LLM with supervised fine-tuning	SPICE simulation
	Artisan [34]	LLM with supervised fine-tuning	SPICE simulation + BO
	Atelier [52]	LLM with RAG	SPICE simulation + BO
	AnalogGenie [53]	Domain-specific GPT trained on analog netlists	SPICE simulation
AMS Design: Layout	LayoutCopilot [54]	Multi-agent LLM (script generation)	Layout scripts (SKILL / Python)
	Masala-CHAI [55]	Vision model + LLM	Schematic-to-netlist accuracy
Physical Design: Script Generation	ChatEDA [56]	LLM + LangChain	Syntax correctness, logical accuracy
	EDAid [57]	LLM + multi-agent (RAG / history)	Debugging logs, interaction history
	MCP4EDA [58]	LLM + backend-aware loop	Tool execution logs, PPA metrics
	JARVIS [59]	LLM + synthetic data augmentation	Synthetic training samples
Physical Design: Placement and Routing	Painting on Place [60]	cGAN, image-to-image	Congestion heatmaps, overflow estimates
	Policy-Gradient [61]	RL + DREAMPlace simulator	Total wirelength (HPWL), DRC violations
	GAN-Place [28]	GAN with style transfer	Macro locations, geometric similarity
	PatternPaint [32]	Diffusion model + litho simulation	Lithography hotspots, DRC rules
Manufacturing: Mask Optimization, Hotspot Correction, and Reliability Modeling	LithoGAN [62]	cGAN	Resist contours, EPE metrics
	EM-GAN [25]	GAN	Electromigration stress maps, IR drop
	Physics-VAE [20]	Physics-integrated autoencoder	Breakdown time, lifetime distribution
	CycleGAN-Hotspot [63]	CycleGAN	Hotspot images, wafer yield
	GridVAE [64]	VAE	IR drop
	GAN-SRAF [65]	GAN	Assist feature placement on layout
	GAN-OPC [66]	GAN	Corrected mask, simulated wafer image

Table 1. Summary of generative AI tools and methods organized by design stage.

Design Stage and Task	Method / Tool	Model and Grounding	Feedback / Signal
Logic Synthesis: RTL Generation and Circuit Construction	ChipChat [41]	LLM + interactive prompting	Verilog code, simulation logs
	DAVE / RTLcoder [42,43]	Fine-tuned LLM	Syntax checks, testbenches
	ShortCircuit [44]	Transformer + MCTS	AIG structure, Boolean equivalence
	T-Net [45]	Triangular network (Shannon decomp.)	Truth tables, logic correctness
	GPT-LS [46]	Decision transformer (offline RL)	Synthesis recipes, QoR metrics
	AISYN [47]	RL-based cut selection	AIG rewriting, area/power
	SOformer [48]	Causal transformer	QoR prediction, trajectory pruning
	Vaegan [26]	VAE-GAN hybrid	Synthetic HLS data, MMD
AMS Design: Topology Selection	AMSnet-KG [49]	LLM + KG-RAG retrieval	Simulation-driven sizing (BO)
	ADO-LLM [33]	LLM-guided Bayesian optimization	Sampling efficiency, FoM
	AnalogCoder [50,51]	LLM and MLLM	SPICE simulation, BO, functionality checks
	LaMAGIC [35]	LLM with supervised fine-tuning	SPICE simulation
	Artisan [34]	LLM with supervised fine-tuning	SPICE simulation + BO
	Atelier [52]	LLM with RAG	SPICE simulation + BO
	AnalogGenie [53]	Domain-specific GPT trained on analog netlists	SPICE simulation
AMS Design: Layout	LayoutCopilot [54]	Multi-agent LLM (script generation)	Layout scripts (SKILL / Python)
	Masala-CHAI [55]	Vision model + LLM	Schematic-to-netlist accuracy
Physical Design: Script Generation	ChatEDA [56]	LLM + LangChain	Syntax correctness, logical accuracy
	EDAid [57]	LLM + multi-agent (RAG / history)	Debugging logs, interaction history
	MCP4EDA [58]	LLM + backend-aware loop	Tool execution logs, PPA metrics
	JARVIS [59]	LLM + synthetic data augmentation	Synthetic training samples
Physical Design: Placement and Routing	Painting on Place [60]	cGAN, image-to-image	Congestion heatmaps, overflow estimates
	Policy-Gradient [61]	RL + DREAMPlace simulator	Total wirelength (HPWL), DRC violations
	GAN-Place [28]	GAN with style transfer	Macro locations, geometric similarity
	PatternPaint [32]	Diffusion model + litho simulation	Lithography hotspots, DRC rules
Manufacturing: Mask Optimization, Hotspot Correction, and Reliability Modeling	LithoGAN [62]	cGAN	Resist contours, EPE metrics
	EM-GAN [25]	GAN	Electromigration stress maps, IR drop
	Physics-VAE [20]	Physics-integrated autoencoder	Breakdown time, lifetime distribution
	CycleGAN-Hotspot [63]	CycleGAN	Hotspot images, wafer yield
	GridVAE [64]	VAE	IR drop
	GAN-SRAF [65]	GAN	Assist feature placement on layout
	GAN-OPC [66]	GAN	Corrected mask, simulated wafer image

Table 2. Data bottlenecks across generative EDA domains and their implications for model design.

Domain	Data Availability	Primary Data Bottlenecks	Model Implications
Logic Synthesis	Moderate	Public RTL datasets are small and narrow in design style, making it difficult to train models that generalize across specification types. Functional correctness labels require testbenches that are expensive to write and rarely open-sourced. Evaluation benchmarks vary across works, preventing direct comparison of reported results.	Models rely on self-generated or synthetic supervision, which limits functional correctness guarantees. Generalization across design families and specification formats is poor. Reported accuracy figures are sensitive to benchmark choice and are difficult to reproduce.
AMS Design	Low	Structured datasets of analog circuit topologies are small and expensive to curate, as each entry requires expert annotation and time-consuming SPICE simulation. Process-specific design knowledge is largely proprietary and not shared across institutions or companies.	Models depend heavily on retrieval-augmented generation (RAG) or domain-specific fine-tuning to compensate for limited training data. Foundation-model scaling is impractical without much larger open datasets. Human expert involvement remains necessary throughout the design loop.
Physical Design	Moderate	Many large-scale placement and routing datasets are generated by proprietary EDA tools under non-disclosure agreements, restricting public access. Open benchmarks cover only a subset of real industrial flows, and the labels (e.g., congestion maps, timing reports) are tool-specific and do not transfer across toolchains.	Models trained on open datasets transfer poorly to industrial toolchains. Academic metrics such as half-perimeter wirelength (HPWL) do not always correlate with real PPA outcomes. Results reported on open benchmarks may not reflect performance on proprietary designs.
Manufacturing, Yield, and Reliability	Low	Defect and failure events are rare in production, so labeled inspection datasets are heavily imbalanced: non-defective samples vastly outnumber defective ones. Fab-internal process data and failure signatures are proprietary and not released publicly. The diversity of failure modes across process nodes and design styles is rarely captured in available datasets.	Severe class imbalance limits the ability of models to detect and characterize rare but critical failure modes. Data augmentation and physics-based simulation are commonly used to compensate, but augmented data may not capture the full range of real failure signatures. Physics-informed or hybrid models are often necessary to produce outputs that are physically meaningful under process variation.

Table 2. Data bottlenecks across generative EDA domains and their implications for model design.

Domain	Data Availability	Primary Data Bottlenecks	Model Implications
Logic Synthesis	Moderate	Public RTL datasets are small and narrow in design style, making it difficult to train models that generalize across specification types. Functional correctness labels require testbenches that are expensive to write and rarely open-sourced. Evaluation benchmarks vary across works, preventing direct comparison of reported results.	Models rely on self-generated or synthetic supervision, which limits functional correctness guarantees. Generalization across design families and specification formats is poor. Reported accuracy figures are sensitive to benchmark choice and are difficult to reproduce.
AMS Design	Low	Structured datasets of analog circuit topologies are small and expensive to curate, as each entry requires expert annotation and time-consuming SPICE simulation. Process-specific design knowledge is largely proprietary and not shared across institutions or companies.	Models depend heavily on retrieval-augmented generation (RAG) or domain-specific fine-tuning to compensate for limited training data. Foundation-model scaling is impractical without much larger open datasets. Human expert involvement remains necessary throughout the design loop.
Physical Design	Moderate	Many large-scale placement and routing datasets are generated by proprietary EDA tools under non-disclosure agreements, restricting public access. Open benchmarks cover only a subset of real industrial flows, and the labels (e.g., congestion maps, timing reports) are tool-specific and do not transfer across toolchains.	Models trained on open datasets transfer poorly to industrial toolchains. Academic metrics such as half-perimeter wirelength (HPWL) do not always correlate with real PPA outcomes. Results reported on open benchmarks may not reflect performance on proprietary designs.
Manufacturing, Yield, and Reliability	Low	Defect and failure events are rare in production, so labeled inspection datasets are heavily imbalanced: non-defective samples vastly outnumber defective ones. Fab-internal process data and failure signatures are proprietary and not released publicly. The diversity of failure modes across process nodes and design styles is rarely captured in available datasets.	Severe class imbalance limits the ability of models to detect and characterize rare but critical failure modes. Data augmentation and physics-based simulation are commonly used to compensate, but augmented data may not capture the full range of real failure signatures. Physics-informed or hybrid models are often necessary to produce outputs that are physically meaningful under process variation.

3. Logic Synthesis

Logic synthesis is among the most mature and automated stages of the digital design flow. Modern tools efficiently transform RTL into optimized gate-level implementations thanks to decades of progress in Boolean optimization, technology mapping, and heuristic-driven search. Compared with placement, routing, or verification, the baseline level of automation in logic synthesis is significantly higher. However, recent advances in generative AI—particularly large language models (LLMs), graph transformers, and reinforcement learning—enable forms of automation that extend well beyond traditional synthesis capabilities. These models aim to infer RTL directly from natural language, construct circuits from functional specifications, learn high-quality synthesis recipes from data, and accelerate solver-based optimization. While early demonstrations show substantial potential, the practical integration of generative models into production flows remains an active research challenge.

3.1. RTL and High-Level Code Generation

LLMs have been widely studied for translating natural language or structured specifications into synthesizable RTL. Early works, such as DAVE [42], demonstrated natural-language-to-Verilog conversion, followed by a range of fine-tuned or prompt-engineered models including [43,67,68,69,70,71,72,73]. These efforts explore hierarchical prompting, multi-stage refinement, and domain-specific fine-tuning to improve correctness.

Conversational design frameworks such as ChipChat [41] demonstrate the feasibility of co-designing real processors using interactive prompting. Figure 4 details the complete flow of ChipChat, a seminal contribution to LLM-assisted hardware design. In ChipChat, an engineer provides natural language specifications and constraints to GPT-4, which generates Verilog and a testbench. A compilation and simulation tool then returns structured feedback at one of four levels—no-failing-nodes (NFN), testbench fail (TF), simulation hard fail (SHF), or always-hard fail (AHF)—and the loop iterates until the design passes. As a case study, the framework was used to co-design QTCore, an 8-bit accumulator microprocessor with a 256-instruction ISA, which was successfully taped out in Skywater 130 nm CMOS. This represents the first reported tapeout of an AI-written hardware design. A benchmark study across eight Verilog tasks showed that GPT-4 performs best among the models tested, GPT-3.5 remains usable, and Bard and HuggingChat prove unreliable. A key finding is that LLMs are most effective when used conversationally with human-provided testbenches and verification feedback, rather than in a one-shot generation mode. ChatEDA [56] takes a complementary approach by attempting to drive a full RTL-to-GDSII flow from natural-language queries, grounding a fine-tuned LLaMA 2 model in EDA tool API documentation to decompose user intent into executable Tcl scripts. Despite promising results, both works reveal the need for stronger functional guarantees and broader generalization across design families.

3.2. Generative Circuit Construction

Beyond code generation, several works aim to directly construct gate-level circuits. GAN-based structures [29] produced varied but often non-functional topologies, motivating more structured approaches. T-Net [45] performs end-to-end synthesis from truth tables using a triangular network informed by Shannon decomposition, achieving high correctness on circuits up to 1200 nodes. ShortCircuit [44] frames synthesis as sequential And-Inverter Graph (AIG) construction using a structurally aware transformer refined through Monte Carlo Tree Search. These approaches illustrate that generative models can learn structural biases intrinsic to the logic networks they target.

While these systems produce promising results on curated benchmarks, scalability to multi-output functions and industrial designs remains an active research direction. LLM-based RTL generators treat synthesis as a language-to-code translation problem, where the main challenge is semantic correctness and alignment with specifications. By contrast, methods such as T-Net and ShortCircuit treat synthesis as structured circuit construction; validity is easier to enforce but scalability becomes the dominant bottleneck, because these models must search an exponentially large space of valid circuit structures and have so far been demonstrated only on circuits with a limited number of inputs and outputs. This distinction matters because the two types of models fail in different ways: language models tend to generate syntactically plausible but functionally incomplete RTL, whereas graph-based models preserve structural validity more naturally but remain confined to smaller or more stylized benchmarks. A useful takeaway is that these methods should not be compared purely by headline correctness numbers; they solve different subproblems under different assumptions.

3.3. Synthesis Flow Optimization

Synthesis flow optimization refers to the automated selection and sequencing of logic optimization passes—such as technology mapping, rewriting, and refactoring—to maximize quality of results (QoR) metrics including area, delay, and power. GPT-LS [46] uses an offline reinforcement learning (RL) Decision Transformer trained on OpenABC-D trajectories, achieving QoR competitive with Bayesian optimization while reducing sequence generation time. AISYN [47] embeds RL-based cut selection within AIG rewriting to target area and power improvements, demonstrating substantial gains on ISCAS’85 circuits and modest improvements on industrial designs.

These works highlight the potential of data-driven policy learning to complement or replace hand-crafted heuristics for synthesis flow optimization.

3.4. Predictive Modeling and Solver Acceleration

Predictive models aim to accelerate synthesis by forecasting QoR outcomes or improving solver efficiency. SOformer [48] employs a causal transformer with cross-attention between circuit graphs and optimization sequences to predict synthesis trajectories, enabling early pruning of low-quality flows. Transformer-based MaxSAT solvers [74] represent conjunctive normal form (CNF) formulas as bipartite graphs and use a graph attention mechanism with multi-relational (meta-path) edges [74] to achieve significant speedups over classical SAT/MaxSAT engines.

Such models illustrate how generative and predictive architectures can augment existing optimization engines and reduce computational overhead across flow iterations.

3.5. System-Level Generative Synthesis

Using GPT-4, the authors of [75] demonstrated an end-to-end generative design of a vector processor SoC, encompassing RTL, firmware, and verification infrastructure; the design was fabricated successfully in 130-nm CMOS. Although a compelling proof of concept, context-length and modularity constraints currently limit generalization beyond designs of this scale and regularity.

Generative approaches have also been explored for data augmentation and design-space exploration. Vaegan [26] produces high-fidelity HLS data using a VAE–GAN hybrid, reducing Maximum Mean Discrepancy by 44% compared to Gaussian or ABC-based generators. Phybrid [76] employs transfer learning to predict ASIC metrics from FPGA prototypes, achieving an average error of 2.6%. These works highlight how generative models can mitigate data scarcity in architecture- and HLS-level exploration.

3.6. Limitations of Current Models and Resource Requirements

Despite rapid progress, substantial challenges remain before generative models can be deployed reliably in industrial logic synthesis flows. Current LLM-based RTL generators often exhibit performance degradation as design complexity increases. Generative circuit construction models such as T-Net and ShortCircuit show promising results on small or medium-scale benchmarks but struggle to scale to larger multi-output functions because the search space grows exponentially with the number of inputs and outputs; training these models also requires considerable GPU resources.

A second challenge concerns data scarcity and limited access to high-quality training data. Public RTL datasets are small, narrow in domain coverage, and often contain inconsistencies. As a result, many works including [42,43,67,69,71,73] assembled their own datasets, which were typically limited in circuit variety and design style, restricting the generalization of the trained models to circuit families not well represented in those datasets. Proprietary datasets, such as those used in ChipNeMo [77], demonstrate the benefits of domain specialization but are not publicly accessible, limiting reproducibility and community-wide progress.

A third challenge is the lack of common evaluation methods across works. Current studies use disparate metrics ranging from Likert-scale human assessments [77] to syntax checks and partial functional testbenches [67,73]. Because researchers are not using a common set of evaluation methods, the results reported across works cannot be fairly compared. The absence of shared benchmarks for RTL generation, circuit construction, and synthesis flow optimization makes it difficult to measure progress or identify which methods represent genuine advances.

Finally, the heavy dependence on proprietary large models and the prohibitive cost of high-quality fine-tuning pose practical barriers. GPT-4 [78] and related closed models continue to outperform existing open-source alternatives, yet their weights are inaccessible for domain-specific refinement. Conversely, strong open-source results such as those achieved by ChipNeMo rely on massive compute budgets—on the order of 128 A100 GPUs—which are far beyond the reach of most academic labs and smaller companies.

A further limitation is that most logic-generation studies are evaluated in isolation from downstream physical design. An RTL or synthesis recipe that appears beneficial under local QoR metrics may still lead to poor floorplanning, congestion, or timing closure later in the flow. This disconnect is especially problematic for LLM-based generators, whose outputs may preserve functional intent while introducing structural patterns that are difficult to route or optimize physically. A more realistic evaluation framework would track whether improvements at the logic stage are preserved through placement, routing, and signoff.

Collectively, these limitations highlight that, although generative AI has introduced new opportunities for logic synthesis, significant challenges related to scalability, dataset quality, evaluation standards, and computational resources must be addressed before such methods can be integrated into industrial design flows.

4. Analog/Mixed-Signal Circuit Design

In contrast to digital design, which has seen maturation of automated design flows, analog/mixed-signal (AMS) circuit design still relies on significant manual effort. Designers iteratively refine and tune their circuits, a process that is not only time-consuming but also dependent on expert intuition, prior experience, and a deep understanding of performance trade-offs when selecting topologies.

Researchers have applied generative AI and machine learning to AMS design with the aim of reducing manual design effort and improving scalability. There are four primary applications of generative AI to analog/mixed-signal design: sizing, topology synthesis, layout, and schematic and document parsing. Analog sizing refers to the optimization of design variables, such as MOSFET channel widths and resistance values, to meet a set of performance specifications. Topology synthesis refers to the selection or generation of a circuit topology. Layout refers to the physical arrangement of circuit components and their connections, performed after topology synthesis and sizing. Schematic and document parsing uses generative models to extract circuit descriptions, component values, and performance specifications from written documents, including data sheets, application notes, and journal papers. Beyond these categories, recent work has also explored the use of generative models for behavioral modeling [79,80,81] and testbench generation [82]. However, the use of generative AI for these purposes remains relatively limited; therefore, we do not discuss them in detail in this survey.

This section surveys the current uses of generative AI in topology synthesis, sizing, layout, and schematic and document parsing, while also discussing current limitations, open issues, and future trends.

4.1. AMS Topology Synthesis

Circuit synthesis is among the biggest hurdles to AMS design automation due to its complex design space containing numerous discrete components of different types and a strong reliance on human expertise. Recent advances in generative AI have opened promising pathways toward automating this process by enabling models to learn high-level structural patterns and generate valid circuit topologies directly from high-level specifications. Broadly, research efforts in generative AI for AMS topology synthesis fall into two categories: (1) use of widely available pre-trained models such as large language models (LLMs), and (2) development of custom generative models such as generative adversarial networks, variational autoencoders, and domain-specific pre-trained models.

4.1.1. LLM-Based Topology Synthesis

Recent progress in LLM-assisted EDA has revealed a key bottleneck for AMS circuits: the lack of high-quality, structured topology data to support model reasoning and prevent hallucination. Shi et al. address this issue with AMSnet-KG, a curated dataset linking AMS netlists to a knowledge graph that encodes architectural semantics, pin functions, and expert annotations [49]. Global annotations guide topology selection, while local annotations mark components that must be treated as matched pairs during sizing, as well as the net connections subject to matching constraints. AMSnet-KG integrates LLMs through Knowledge-Graph Retrieval-Augmented Generation (KG-RAG) to enable automated AMS circuit generation. Given performance specifications, the LLM proposes a high-level design strategy, which is used to retrieve matched components and testbenches from AMSnet-KG. The system then assembles a candidate topology and performs simulation-driven sizing using Bayesian optimization. If specifications are unmet or the estimated number and size of transistors exceeds a user-specified threshold, the framework iteratively refines and regenerates the topology, closing the loop with minimal human intervention.

Rather than taking a RAG approach, the developers of LaMAGIC opted to fine-tune an LLM using a custom dataset of power converter circuits [35]. The objective of LaMAGIC is to generate power converter topologies in a single forward pass. To improve generation quality, LaMAGIC introduces a structured prompt format referred to as the canonical form. These enhancements enable LaMAGIC to generate correct topologies with a 96% success rate, outperforming prior reinforcement learning-based methods.

Similarly, Artisan employs a purpose-built dataset of three-stage operational amplifier topologies to fine-tune a 7B-parameter LLM [34]. In addition to supervised fine-tuning, Artisan incorporates a custom chain-of-thought and tree-of-thought prompting scheme for three-stage amplifier topology generation. It also introduces a textual circuit representation called NetlistTuple, which converts the conventional graph-based circuit description into a text format more suitable for LLM processing. A key limitation of fine-tuning, as demonstrated in both Artisan and LaMAGIC, is the substantial computational cost required for training. Fine-tuning also produces models that are narrow in scope: a model trained on three-stage amplifiers cannot readily be applied to other circuit families without retraining on a new dataset.

Atelier also targets the synthesis of three-stage operational amplifiers but takes a different approach to address the data problem [52]. Rather than fine-tuning, the developers of Atelier constructed a custom database of circuit topologies extracted from published circuit papers and data sheets using LLMs, and integrated it with RAG and open-source LLMs. Atelier further employs a multi-agent, feedback-based design flow with graph-of-thought prompting, achieving better performance in three-stage amplifier topology generation than Artisan. The comparison between Artisan and Atelier suggests that RAG-based approaches can match or exceed the accuracy of fine-tuned models on specialized tasks while avoiding the high training cost and narrow generalization of fine-tuning. However, RAG-based methods depend on the quality and coverage of the retrieval database, and their performance may degrade on circuit families that are not well represented in the database. AnalogCoder [50] and AnalogCoderPro [51] take a different direction from all of the previous methods. Instead of building a knowledge database or fine-tuning a model, these tools reframe topology selection as a Python code generation problem. This strategy leverages the LLM’s code-generation capability while avoiding the time-consuming database construction required by RAG-based methods and the computational cost of fine-tuning. A feedback loop informed by circuit simulation is used to verify that the generated topologies are functional. Figure 5 presents the full AnalogCoderPro framework, which extends this by using a multimodal LLM that can accept simulation waveform images as input, feeding visual simulation results back into the multi-agent design loop [51].

Collectively, these LLM-based approaches illustrate a trade-off between breadth and specialization in AMS topology synthesis. Methods such as AnalogCoder and AMSnet-KG support a wide variety of circuit types, but often struggle to produce highly optimized circuits. In contrast, Artisan, Atelier, and LaMAGIC focus on narrow circuit classes such as three-stage operational amplifiers or power converters, achieving higher success rates within those domains but lacking generality. Because these two groups of methods are evaluated on different tasks and by different metrics, their reported results are not directly comparable. What is clear is that both directions are being actively explored; what remains unknown is which approach will ultimately yield better results as circuit complexity increases and evaluation methods become more standardized.

4.1.2. Custom Generative Models

In contrast to approaches that rely on widely available LLMs, the works discussed in this section employ custom deep-generative models. The first class integrates generative models within the optimization loop, as in [83] and [84], to generate amplifier topologies from specifications. The second class uses generative models to directly synthesize topologies.

The work in [83] generates amplifier topologies using a graph variational autoencoder (G-VAE) combined with a Bayesian optimizer. Since many Bayesian optimization algorithms are designed for continuous design spaces, the authors first learn a G-VAE that embeds the discrete, graph-encoded circuit description of a three-stage amplifier into a continuous latent space. After optimizing the topology, they map the result to a transistor-level implementation using a library of building blocks and the $g_m/I_D$ methodology. Similarly, ATOM [84] represents the three-stage amplifier as a directed acyclic graph (DAG) and uses a DAG-VAE to embed the graph into latent space. By combining this embedding with an improved freeze-thaw Bayesian optimization algorithm, ATOM achieves higher success rates while requiring up to $8.5\times$ fewer simulations than prior state-of-the-art methods.

AnalogGenie [53] takes a more general approach by training a domain-specific GPT model on a dataset of over 3,000 analog circuit topologies. It introduces a novel circuit representation based on an Eulerian circuit traversal and a custom tokenizer designed for circuit netlists. After fine-tuning, AnalogGenie produces valid topologies for 93.2% of generation attempts across a diverse range of circuit types.

In summary, the G-VAE and ATOM approaches demonstrate the effectiveness of embedding generative models within optimization frameworks for topology generation, but remain tailored to specific circuit types. AnalogGenie represents a step toward more general and scalable topology generation by training on a broader and more diverse dataset.

4.2. AMS Circuit Sizing

Machine learning-based tools have been widely used for analog circuit sizing—optimizing design variables to meet specific performance requirements. Prior approaches using black-box optimization techniques such as Bayesian optimization (BO), reinforcement learning, and deep learning often lack awareness of circuit topology or domain knowledge. The papers in this section address this limitation by incorporating LLMs into the optimization process to inject circuit-specific knowledge.

ADO-LLM explores the integration of LLMs with BO to improve sampling efficiency in analog circuit design [33]. The approach uses the in-context learning ability of LLMs to inject domain knowledge into the BO process, refining candidate samples generated by the optimizer. The method produces high-quality design points efficiently across two different types of analog circuits, achieving improvements in both design efficiency and solution quality. However, the framework is constrained by its reliance on external LLM APIs and the inherent curse of dimensionality faced by BO in high-dimensional design spaces.

LEDRO introduces a different strategy by combining LLMs with BO for design space reduction rather than direct point selection [85]. The framework employs a 70B-parameter LLM to identify the regions of the design space most likely to contain high-performance solutions, thereby guiding subsequent BO searches. The approach achieves superior figure of merit (FoM) performance and requires fewer iterations to converge for both simple and complex op-amp designs.

EasySize adopts a different strategy compared to LEDRO and ADO-LLM [86]. Instead of narrowing the design space, it uses an LLM to determine the weighting of performance metrics within an FoM-based optimizer. The method first ranks performance metrics based on how easily their requirements can be met. A set of design specifications is then generated, and corresponding loss functions are created with weightings derived from ease of attainability and human feedback. This dataset is used to fine-tune the LLM, which then generates optimized FoM weights for the sizing optimizer. The authors report superior sizing performance compared to prior BO-based methods on a set of op-amp benchmarks; however, comparisons to other state-of-the-art sizing methods and evaluations on more complex circuit types have not yet been reported.

Despite these promising results, the generalizability of LLM-guided sizing remains unclear, and further comparison with other state-of-the-art methods across a broader range of circuit types is needed. An interesting future direction is the integration of sizing feedback into the topology generation tools discussed in the previous section, which would help close the loop between topology selection and parameter optimization.

4.3. Analog Layout

Analog layout design remains a largely manual process due to complex constraints on symmetry, matching, and parasitic sensitivity that strongly influence post-layout performance. Automating this process is challenging, as the quality of results from tools like MAGICAL or ALIGN depends heavily on parameter tuning and the correct definition of layout constraints. Even interactive layout environments suffer from similar limitations, as user-defined constraints and parameter choices can significantly affect layout quality. Recent research has begun exploring how machine learning and LLMs can enhance analog layout automation and interactivity by improving constraint specification and designer–tool collaboration.

Chen et al. integrate LLMs with Bayesian optimization to address the problem of net weighting constraints in the MAGICAL layout tool [87]. In MAGICAL, net weights control the priority assigned to different signal nets during placement and routing; setting these weights correctly is critical to achieving good layout quality but requires expert knowledge. Their method uses the in-context learning ability of an LLM to perform key BO steps, including initializing design points, modeling the design space, and selecting new candidate points. The approach achieves performance comparable to state-of-the-art BO algorithms while enabling more effective design space exploration. However, repeated LLM inference introduces significant computational overhead, raising concerns about scalability to larger designs.

LayoutCopilot takes a complementary approach by improving the usability of interactive layout tools rather than pursuing full automation [54]. It generates layout scripts from high-level natural language commands, handling tasks such as constraint generation and parameter adjustment for device placements. LayoutCopilot employs a multi-agent system that decomposes user commands into executable layout scripts, with specialized agents handling subtasks such as code generation, task decomposition, and abstraction classification.

Other generative approaches target specific layout subproblems. Wang et al. propose a generative learning framework for analog building-block layout that leverages prior design data [88]. Layouts from a design repository are used to train a variational autoencoder (VAE) that captures designer layout preferences across multiple block types. The trained model then generates routing guidance for new layouts, improving circuit performance by 1.2% in gain and 2.1% in bandwidth compared to traditional migration-based methods.

Analog layout optimization also requires joint consideration of N-well/P-well region generation and device placement to prevent area inefficiency, parasitic coupling, and the Well Proximity Effect (WPE). Traditional placers treat wells as post-processing constraints, but Zhu et al. propose a well-aware placement approach that integrates well generation directly into placement by modeling wells as fence-region constraints [89]. A conditional GAN generates well guidance masks from initial placements, steering the placer and enforcing the WPE constraint during legalization to maintain compact layouts and low half-perimeter wirelength (HPWL). The method achieves up to 82% area reduction and 46% HPWL reduction over baselines. Remaining challenges include scalability to larger circuits, adaptability across process nodes, and dependence on manually optimized training data.

4.4. Schematic and Document Parsing

Recent work in analog design automation has emphasized the importance of scalable, structured data generation to support data-driven design methods. Much of the most valuable information about AMS circuits has been presented in the form of schematic images, which are not suitable inputs for many automation tools. Similarly, performance specifications and design parameters are often buried in written documents such as data sheets and journal papers, making them difficult to ingest into automated design flows.

Masala-CHAI addresses the schematic parsing problem through the creation of a large-scale dataset that bridges schematic images and circuit-level representations via netlists [55]. By combining a YOLOv8-based vision pipeline with an LLM, the tool automatically identifies circuit components in schematic diagrams and translates them into SPICE netlists. It employs advanced prompt tuning to enhance netlist extraction accuracy, thereby reducing component classification errors, incorrect node assignments, and missing elements. Note that AMSnet-KG similarly automates the process of deriving netlists from schematic images; however, a different vision pipeline was used to identify and label components in the schematic images [49].

A complementary tool, DocEDA, translates human-authored documents, such as conference papers and data sheets, into formalized specifications suitable for automated design workflows [90]. DocEDA combines computer vision with chain-of-thought LLM prompting to parse figures, tables, and text and extract circuit specifications such as gain, bandwidth, and supply voltage. This capability supports dataset expansion and improves interoperability between written design documents and machine learning-based analog design tools.

4.5. Trends, Limitations, and Future Directions

Recent progress in generative AI for analog circuit design highlights promising directions, but several key challenges remain. One limitation is the lack of methods that close the loop between topology, sizing, and layout. In practice, layout failures are often discovered late in the design flow, and current tools do not provide mechanisms to feed layout outcomes back into topology synthesis or sizing decisions. Similarly, few works utilize feedback between sizing and topology synthesis.

Another barrier is the scarcity of high-quality training data. Constructing circuit datasets remains labor-intensive, requiring extensive domain expertise, and few efforts have focused on systematically open-sourcing such resources. Broader community-driven initiatives in data collection and sharing could accelerate progress, lower the entry barrier for new researchers, and promote reproducibility.

The field also lacks widely adopted open benchmarks, making it difficult to compare results across works. Many current methods are evaluated on narrow circuit classes or relatively simple design problems, making it hard to assess scalability to more complex scenarios. Establishing standardized benchmarks would enable more rigorous evaluation of generative models in AMS design. Some initial steps have been taken: AnalogGym provides an open sizing benchmark based on open-source PDKs [91], and AMSnet-KG has been partially open-sourced [49].

Finally, robustness to process, voltage, and temperature (PVT) variation and device mismatch remains largely unaddressed. Most existing methods focus on nominal design conditions, leaving a gap in ensuring reliable performance under real-world variability. Addressing this limitation is essential for transitioning these techniques into practical design automation tools.

5. Physical Design

In this section, we focus on the domain of IC Physical Design. Recent advances in Generative AI have also led to a number of innovative studies in this field. We categorize its major applications into two main areas.

5.0.1. Tool Script Generation

Generative models have achieved notable breakthroughs in recent years. Large Language Models (LLMs) are rapidly transforming their ability to comprehend tool documentation and autonomously generate scripts into substantial productivity improvements in EDA tool automation.

5.0.2. Placement and Routing

Generative models are increasingly employed to capture spatial and topological correlations in physical layouts. Approaches such as conditional GANs, diffusion models, and reinforcement–generative hybrids have been leveraged to enhance placement quality, predict routing congestion, and generate DRC-compliant layout patterns, demonstrating the capability of generative modeling to explore diverse, physically consistent design solutions beyond traditional heuristic optimization.

5.1. Tool Script Generation

One of the key challenges in Physical Design (PD) is the efficient utilization of Electronic Design Automation (EDA) tools, which often requires engineers to interpret and translate complex user guides, command references, and tool manuals into executable scripts. Leveraging their strong language comprehension and code-generation capabilities, Large Language Models (LLMs) have recently demonstrated remarkable effectiveness in this area—particularly in automating and optimizing EDA scripting workflows.

5.1.1. First Stand alone

Early progress was made by Bei Yu et al., who introduced ChatEDA [56] at MLCAD 2023. Figure 6 illustrates the complete ChatEDA framework for LLM-driven RTL-to-GDSII automation. ChatEDA employed LLaMA 2 as the base model and applied LoRA fine-tuning to adapt it to OpenROAD [92] commands and APIs. The OpenROAD ecosystem itself integrates several key open-source components—including Yosys [93] for RTL synthesis and OpenLane [94] for full RTL-to-GDSII flow automation—providing a complete, open testing environment for LLM-driven physical-design automation. By fine-tuning on domain-specific scripting data, ChatEDA aligned the generative capabilities of the model with the structured syntax and hierarchical logic of EDA commands. This made LLaMA 2 particularly suitable for the task: its large contextual window and natural-language reasoning ability allowed the model to interpret high-level design intents and translate them into executable Tcl scripts, effectively bridging the gap between user intent and tool operation.

5.1.2. Multi-agent collaboration

Building upon this foundation, the same research group proposed EDAid [57], a multi-agent collaborative framework that integrates several domain-specialized LLM agents. Each agent focuses on a different stage of the EDA flow—such as synthesis setup, placement control, or verification script generation—and cooperates through message passing and task decomposition. This multi-agent architecture fits the problem of multi-stage flow orchestration naturally, as it mirrors how human experts coordinate across specialized tool domains. By distributing reasoning responsibilities among specialized LLMs, EDAid improved both the reliability and contextual accuracy of generated scripts, achieving higher success rates in complex hierarchical flows.

5.1.3. Close-loop feedback

More recently, MCP4EDA [58] further advanced this paradigm by introducing result-aware automation and parameter optimization. Unlike earlier models that generated scripts in a static, one-shot manner, MCP4EDA established a closed-loop feedback mechanism between the LLM and the EDA toolchain. It incorporated real backend feedback—such as timing, area, and congestion metrics—into iterative synthesis optimization, allowing the model to refine its script generation based on physical outcomes. This framework employed Retrieval-Augmented Generation (RAG) to ground the model in tool documentation and synthesis heuristics, while leveraging its generative capabilities to explore new combinations of optimization parameters. The integration of retrieval grounding with backend feedback made the model both contextually aware and physically meaningful, achieving measurable improvements in timing and area across multiple RTL-to-GDSII benchmarks.

5.1.4. Data augmentation

While these academic contributions demonstrate the feasibility and promise of LLM-based EDA automation, they are largely constrained by their reliance on open-source tools and datasets. This dependence limits their evaluation scope and generalizability to proprietary industrial environments, where tool ecosystems, parameter spaces, and design rules are significantly more complex. To tackle this, NVIDIA’s research team introduced JARVIS [59] in 2025—a multi-agent code assistant designed for high-quality EDA script generation. JARVIS advances the field by employing Synthetic Data Generation (SDG) to augment limited training data and performing both Domain-Adaptive Pre-Training (DAPT) and Domain-Supervised Fine-Tuning (DSFT) to enhance the model’s understanding of specialized API structures. It further integrates the strengths of prior academic frameworks—multi-agent collaboration and feedback-guided correction—within an industrial-grade setting, achieving more robust and verifiable script generation. Through the combination of data synthesis, retrieval-based grounding, and structured multi-agent reasoning, JARVIS represents a pivotal step toward scalable, enterprise-level deployment of generative EDA assistants.

Collectively, these works address the challenge of automating EDA tool control by employing generative LLM architectures that are structurally aligned with the problem itself: their text-to-code reasoning enables high-level design specifications to be translated into executable flow scripts, while their generative adaptability supports iterative optimization and tool parameter exploration. This evolution—from static script generation to context-aware, feedback-driven automation—marks a significant step toward intelligent and adaptive physical-design flows.

5.2. Placement and Routing

Within the overall Integrated Circuit (IC) Physical Design flow, generative models have indeed demonstrated remarkable potential in tool control and script generation. However, due to the inherently diverse nature of tasks across different stages, the impact of generative modeling remains concentrated in only a subset of domains—most notably in standard cell library generation, floorplanning, placement, and routing. These stages naturally involve design-space exploration and multi-solution search, where the capacity of generative models to synthesize diverse and physically consistent alternatives becomes particularly advantageous.

5.2.1. Congestion awareness Placement

One of the earliest applications of generative modeling in physical design appeared in Painting on Placement [60], which addressed the problem of routing congestion prediction. Traditional analytical or regression-based congestion estimators require handcrafted features and lack spatial generalization. To overcome this, the authors reformulated congestion estimation as a conditional image-to-image generation task and employed a conditional Generative Adversarial Network (cGAN) to translate placement maps into predicted congestion heatmaps. This model fits the problem naturally, since both placement layouts and congestion maps are spatially structured data. By learning a direct mapping from spatial cell-density distributions to congestion patterns, the conditional GAN provided a fast, differentiable, and layout-aware alternative to classical estimators, significantly accelerating early-stage routability analysis.

5.2.2. Routability awareness Placement

Building on this concept of generative spatial prediction, Cheng et al. proposed the Policy-Gradient Placement and Generative Routing framework [61], which jointly tackled macro placement and global routing. They introduced a hybrid architecture that combined a policy-gradient reinforcement learning (RL) network for macro placement with a conditional generative routing model that produced one-shot routing paths. The RL component was used to sequentially decide macro positions under multi-objective physical constraints, while the generative routing model directly synthesized valid interconnect paths conditioned on pin locations and net topology. This design tightly couples the model structure with the physical problem: the sequential decision nature of placement aligns with reinforcement learning, while the spatially structured routing generation benefits from the conditional generative approach. Such synergy enabled improved wirelength, routability, and congestion balance compared with traditional heuristic or sequential routing methods.

5.2.3. Style Transfer for Layout Distribution

More recently, GAN-Place [28] extended adversarial learning to the standard-cell placement problem. Rather than generating new layouts from scratch, GAN-Place adopted a style-transfer–based adversarial framework to inject the spatial distribution characteristics of high-quality placements into existing open-source placers. Here, the generator learns the implicit “style” or statistical distribution of expert-designed layouts, while the discriminator enforces structural plausibility and density constraints. This adversarial setup fits the nature of placement optimization, where the goal is not purely reconstruction but distribution matching between generated and optimal placements. By aligning the generative model’s output distribution with high-performance design samples, GAN-Place demonstrated consistent improvements in placement quality and PPA (Power–Performance–Area) metrics.

5.2.4. DRC Rule Compliance Placement and Data Augmentation

At the pattern and manufacturability level, PatternPaint [32] addressed the problem of layout pattern augmentation for Design for Manufacturability (DFM) and lithography hotspot analysis. The authors used a combination of inpainting and diffusion-based generative models to synthesize new, rule-compliant layout patterns that expand the coverage of existing pattern libraries. Diffusion models were particularly suitable for this task, as their iterative denoising process allows the generation of fine-grained geometric details while preserving DRC-compliant spatial relationships. This work demonstrated that generative modeling can complement traditional pattern-matching or rule-based verification methods by producing realistic, manufacturable variants that enrich training datasets for DFM and lithography analysis.

In contrast, stages such as clock tree synthesis (CTS) [95], signoff analysis, power integrity evaluation, and DRC/LVS verification have seen relatively limited adoption of generative modeling. These tasks are inherently deterministic and constraint-driven, focusing on producing a single correct and convergent solution that satisfies strict physical and electrical rules. Consequently, rule-based and discriminative learning approaches remain dominant in these domains, as they emphasize prediction accuracy and constraint satisfaction over design-space exploration. Thus, while generative frameworks excel in creative, exploratory, and data-scarce tasks within the PD flow, deterministic models continue to serve as the backbone for analysis-oriented stages such as timing closure and physical signoff.

5.3. Trends, limitations, and future directions

While generative modeling has shown considerable promise across multiple domains of Physical Design, significant challenges remain before these methods can achieve practical and generalizable solutions. In the area of EDA tool script generation, recent works have demonstrated impressive progress in automating tool operation and parameter tuning. However, most academic efforts still rely heavily on open-source tools and datasets, which inevitably limits their transferability and compatibility with proprietary industrial flows. Moreover, the absence of a standardized, third-party benchmark for script generation and tool control makes it difficult to perform fair and reproducible comparisons—many studies report strong results under inconsistent or domain-specific evaluation settings. The establishment of open, unified benchmarks and metrics for evaluating generative EDA assistants will be essential to move beyond proof-of-concept results toward systematic performance assessment.

Within the Physical Design workflow, generative models have proven particularly effective in placement and routing, where design-space exploration and distribution learning are central to the problem structure. Nevertheless, the direction of modern EDA development is increasingly toward cross-stage integration, in which early steps such as logic synthesis and floorplanning are executed with full awareness of downstream objectives including timing closure, power optimization, and signal integrity. This trend amplifies the computational and modeling burdens of early PD stages, as these tasks must implicitly account for complex multi-physics and cross-layer dependencies. In this context, generative AI stands out as a key enabler: by learning comprehensive, multi-domain representations and fine-tuning on high-quality, cross-stage datasets, generative models can serve as powerful surrogates and design-space explorers that capture inter-stage interactions more effectively. Such integration has the potential to not only accelerate early-stage decision-making but also propagate improvements downstream, ultimately enhancing the overall efficiency and intelligence of the physical design flow.

The same argument applies downstream. Placement and routing are often evaluated using HPWL, congestion, or timing-oriented proxies, yet these objectives do not fully capture manufacturability risk. A placement policy that improves routability may still increase hotspot density or complicate mask correction. This suggests that cross-stage integration in generative PD should not stop at logic-aware optimization, but should also incorporate lithography and reliability feedback earlier than is common today.

6. IC Yield and Reliability

Generative AI has emerged as a valuable tool in yield and reliability analysis, addressing persistent challenges in defect detection, reliability prediction, and lithography optimization. These three areas are traditionally among the most data- and compute-intensive tasks in semiconductor manufacturing. At their core, they share common bottlenecks: (i) labeled data are scarce and highly imbalanced, particularly for rare but critical defect and failure modes; (ii) physical parameters such as electric fields, stress maps, or resist contours must satisfy underlying physics constraints to be meaningful; and (iii) physics-based simulation flows, while accurate, are prohibitively slow for industrial-scale deployment. Generative frameworks are typically employed to model the distributions of these key physical parameters—such as voltage drop maps, defect patterns, or lithographic contours—and then integrate these with domain equations or heuristic models for downstream analysis. This dual role of generative modeling, as both data augmenter and physics surrogate, explains much of its growing appeal in IC yield and reliability research.

6.1. Data Augmentation

One of the most universal challenges across IC design and manufacturing is the lack of labeled data. In wafer inspection and defect classification, images of defective wafers form only a tiny fraction of all collected inspection data, leading to heavily skewed datasets. Traditional augmentation strategies—rotations, flips, random crops—expand dataset size but do little to diversify underlying defect signatures. Generative AI provides richer augmentation by synthesizing entirely new images of wafer defect patterns. In [96] and [97], VAEs were trained to generate synthetic wafer defect images. VAEs learn a continuous latent representation of the defect distribution and sample from it to produce new examples; this makes them well suited to generating diverse variations of rare defect types, but the reconstruction-based training objective can lead to blurry outputs that may not capture fine-grained defect morphology. By augmenting training data with these synthetic samples, the authors achieved significant gains in fault classification accuracy, with improvements of up to 40% in some defect categories [97].

In contrast to VAE-based approaches, GAN-based models produce more visually sharp and realistic defect images because the adversarial discriminator explicitly penalizes outputs that do not resemble real defects. However, GANs can be harder to train and are more prone to mode collapse, in which the generator produces only a limited variety of outputs. For wafer inspection tasks, GAN-based models were shown to generate realistic defect maps that strengthened the robustness of downstream classifiers, especially against rare defect types [98].

The challenge of small-sample learning is equally pressing in analog and mixed-signal circuits, where circuit faults may only be observable under certain test conditions. Jia et al. combined Deep Convolutional GANs (DCGANs) with Transformer architectures to generate time-frequency fault signatures, enabling accurate detection of soft faults despite limited labeled data [99]. These works collectively show that generative AI can function as a “data equalizer,” mitigating class imbalance and enabling the use of conventional classifiers in otherwise data-sparse regimes.

Beyond defect detection, post-silicon reliability analysis also benefits from generative augmentation. Carbunescu-Stoenescu et al. used VAEs to reconstruct multivariate parameter distributions from small post-silicon datasets, supporting accurate yield estimation despite data scarcity [100]. Yan et al. further advanced this approach by integrating semantic autoencoders with a physics-based percolation model of gate oxide breakdown, allowing dielectric thickness distributions to be inferred directly from measured dielectric lifetime distributions [24]. Figure 7 provides a detailed overview of the semantic autoencoder framework for dielectric lifetime modeling. This physics-informed generative approach not only produced more accurate lifetime distribution estimates but also improved interpretability by aligning predictions with the physics of dielectric wearout. Through a physics-embedded decoder, it can generate trustworthy synthetic data to support large-scale reliability analysis. Follow-up work refined the loss functions used in training, tightening prediction intervals and producing physically meaningful parameter distributions [101]. These examples underscore how generative autoencoders provide an alternative to traditional statistical fitting and Monte Carlo simulation for yield and lifetime estimation.

6.2. Defect Localization and Spatio-Temporal Modeling

While dataset augmentation mitigates data scarcity, accurately modeling the spatial location and temporal evolution of defects and mechanical stresses remains a critical challenge that often exceeds the capabilities of conventional rule-based analysis. Generative methods increasingly move beyond binary “defective vs. non-defective” classification toward pixel-level defect segmentation—the task of identifying the precise location and extent of each defect within an inspection image—and temporal stress prediction. In inspection tasks, SEM-based imaging is complicated by noise and the high cost of annotation. Diffusion models have been employed to reconstruct “defect-free” baseline images and then isolate defects as residuals, enabling pixel-level segmentation under weak supervision [31]. Knowledge-distilled variants of these diffusion models, in which a smaller student model is trained to mimic the outputs of the full diffusion model, further reduce inference times by one to two orders of magnitude [31], a key step toward industrial feasibility.

In the context of defect localization, multimodal integration serves as a key enabler for correlating spatial information from different inspection sources. Adversarial learning has been leveraged to achieve such integration: Kim et al. used conditional GANs to combine SEM and layout information, allowing systematic defects—linked to design patterns—to be distinguished from random particle-induced defects [102]. Such integration reflects a trend where generative AI is no longer an add-on but a core part of the inspection pipeline.

Generative AI for spatio-temporal modeling is equally important in reliability. Traditional finite-element solvers for electromigration (EM) and time-dependent dielectric breakdown (TDDB) require hours or days to simulate stress evolution across interconnects. GAN-based frameworks such as EM-GAN recast this as an image-to-image translation problem: given interconnect topologies and current density maps, the model generates stress distributions at different stages of aging [25]. This approach provides large speedups while retaining fidelity to stress physics. Because the GAN is trained to produce outputs that match the spatial structure of finite-element solutions, it functions as a generative surrogate: unlike a regression model that produces a single scalar output, the GAN produces a full two-dimensional stress map that can be used in the same way as a simulation result. Zhou et al. extended the concept with GridNet, which not only predicts EM-induced IR drop but also computes sensitivity maps for localized engineering-change-order fixes, embedding generative prediction directly into the design-optimization loop [103].

GridVAE [64], a VAE-based surrogate model, improved prediction stability and reduced error by nearly 40% compared to prior methods, while achieving over 100× acceleration in full-chip EM-aware IR-drop analysis. Similar principles have been applied to dielectric breakdown modeling, where Lamichhane et al. developed a GAN-based electrostatic solver that accelerates TDDB field calculations by 200× compared with finite-element methods, maintaining near-physical accuracy [104]. This trend also extends to coupled power–thermal settings [105,106]. These works illustrate how generative models function not only as data augmenters but also as computational surrogates, replacing or accelerating traditional solvers while producing outputs that respect underlying physical constraints.

6.3. Mask Optimization and Lithography Modeling

Lithography represents one of the most computationally demanding stages of the IC design flow, where small improvements in mask optimization or hotspot correction translate into large yield gains. Generative models have been widely adopted as surrogates to replace costly optical simulations. Sim et al. pioneered the use of CycleGAN for hotspot correction, formulating the task as unpaired image-to-image translation: hotspot patterns are directly transformed into corrected non-hotspot patterns, eliminating the need for paired training data and reducing correction times from days to hours [63]. Yang et al. proposed GAN-OPC, which combines GANs with inverse lithography pretraining to produce masks that are already near-optimal and require minimal refinement [66].

Similarly, Alawieh et al. introduced GAN-SRAF, which formulates subresolution assist feature (SRAF) insertion as a translation problem and employs novel heatmap encodings to achieve over 100× runtime reduction compared with model-based methods [65]. Ye et al. further developed LithoGAN, an end-to-end conditional GAN that maps masks directly to resist contours, bypassing both optical simulation and contour extraction. LithoGAN achieved accelerations of ∼1800× relative to rigorous solvers [62], highlighting the potential of generative AI for lithography. These works demonstrate how generative methods compress traditionally slow lithography flows into real-time or near-real-time pipelines, enabling their integration into design-stage verification and correction.

6.4. Generative and Physics-Aware Modeling for Packaging Yield and Reliability

Packaging-aware yield and reliability are emerging as central challenges as chiplet-based systems shift critical failure modes beyond the monolithic die into the package, interposer, and die-to-die (D2D) interconnect. The standardization of UCIe has accelerated this transition by enabling package-level interoperability while pushing toward higher data rates (48/64 GT/s), 3D integration, and enhanced reliability features, thereby increasing sensitivity to routing topology, bump architecture, power delivery, and thermal gradients [107,108]. In this context, heterogeneous-integration roadmaps increasingly emphasize packaging as a multiphysics co-design problem, where signal integrity (SI), power integrity (PI), thermal effects, and thermo-mechanical reliability must be addressed jointly rather than in isolation [109,110].

These trends align naturally with the rise of physics-aware surrogate and generative modeling frameworks. Early efforts in packaging have demonstrated the value of fast, parameterized models that bridge traditionally disjoint design stages. For example, optimization of decoupling-capacitor placement across hierarchical PDNs enables tighter coupling between package design and voltage-noise constraints [111], while surrogate-based approaches to interposer design facilitate efficient exploration of routing, shielding, and SI tradeoffs under process variation [112]. Similarly, temperature-dependent RLGC/SPICE representations provide a pathway to unify electromagnetic channel extraction with circuit-level evaluation for chiplet-package co-design, and recent work incorporating temperature, process variation, and yield into UCIe channel design highlights the strong coupling between operating conditions and reliability-optimal design points [113]. Collectively, these approaches point toward the need for compact, physics-grounded models that can support rapid design-space exploration under realistic operating constraints.

Recent literature further reinforces this direction while moving toward more scalable, data-driven paradigms. Techniques such as SPIRAL+ demonstrate that high-speed inter-chiplet validation increasingly requires joint SI/PI analysis rather than isolated channel evaluation [114], while learning-based approaches such as GNN-SP enable fast S-parameter estimation for UCIe-style interconnects, making early-stage exploration tractable [115]. At the system level, multi-fidelity thermal modeling frameworks and electrothermal co-optimization techniques highlight the importance of capturing hotspot formation, PDN behavior, and reliability-sensitive gradients throughout the design process, rather than only at signoff [116].

Taken together, these developments position advanced packaging as a natural next frontier for the physics-aware generative frameworks discussed in this review. In the near term, surrogate and hybrid models can act as fast digital twins for SI/PI, thermal, and yield closure across the package-design space. Looking forward, physics-integrated generative models offer the potential to directly synthesize interposer routing, shielding structures, bump and ground patterns, and PDN decoupling strategies under explicit reliability constraints, extending prior work on physics-aware learning and generative modeling toward full-stack package co-design [117].

6.5. Trends, Limitations, and Future Directions

Each model family discussed in this section addresses a distinct aspect of the yield and reliability problem. Variational autoencoders (VAEs) are well suited to distribution learning under data scarcity because their probabilistic latent space allows new samples to be drawn from the learned distribution even when training data are limited. GANs are effective for generating realistic defect maps and spatio-temporal stress distributions because the adversarial training objective directly encourages outputs that are indistinguishable from real physical data. Diffusion models have demonstrated strong performance for pixel-level defect segmentation because their iterative denoising process preserves fine spatial detail better than reconstruction-based methods. Taken together, these complementary strengths suggest that the field is moving from isolated data augmentation toward tightly integrated, physics-aware workflows in which different model families are combined to address different parts of the problem.

Nevertheless, limitations remain. Many published works continue to rely on VAEs and GANs, which were introduced more than a decade ago. The continued dominance of these models is not inherently a problem—they remain well matched to the image-structured data common in yield and reliability tasks—but it does mean that more recent architectural advances have not yet been fully exploited. Although recent studies have begun exploring the use of large language models [118], LLMs are primarily designed for text and code and there is no strong reason to expect them to outperform image-based generative models on tasks such as defect inspection or lithography correction that are fundamentally spatial in nature. Diffusion models, on the other hand, are a more natural candidate for improvement in these domains: their iterative denoising process can generate high-resolution spatial outputs with fine-grained detail, and conditional variants can be guided by layout geometry or process parameters to produce physically plausible results. Early evidence from defect segmentation tasks supports this expectation [31].

A second limitation is that most frameworks assume the accuracy of the underlying physics equations they interface with. In practice, process physics models are incomplete or approximate, which constrains the reliability of generated outputs. One promising direction is physics-integrated generative modeling, where neural networks are trained jointly with or in correction of physics-based equations, as demonstrated in physics-integrated VAEs [20]. Emerging models such as Kolmogorov–Arnold Networks (KANs) [119] further expand this space by learning functional relationships directly from data in cases where no closed-form equation is available.

Finally, data efficiency remains underexplored. Active learning methods, which adaptively select the most informative samples for labeling or simulation, could substantially reduce the amount of training data required, especially in domains where silicon measurement campaigns are costly. Yet few studies have incorporated active learning [120,121] into generative AI for yield and reliability. Addressing these gaps—adopting more capable generative architectures where appropriate, embedding physics priors more rigorously, and integrating data-efficient strategies—will be critical for next-generation yield and reliability tools.

In summary, the integration of generative AI into IC yield and reliability analysis reflects a broader shift: from ad hoc data augmentation to physics-informed, computationally efficient frameworks that model the full distribution of physical outcomes. As methods mature, the potential exists to scale these approaches to full-chip inspection, cross-node generalization, and hybrid physics–AI simulations, embedding generative models as standard components of semiconductor design and manufacturing workflows.

7. Conclusions

This survey examined generative AI tools across the full silicon lifecycle. We organized recent work by what is generated—circuits, scripts, layouts, masks, surrogates—and by how generation is grounded in retrieval, simulators, and physics, linking AMS, logic, physical design, and manufacturing to datasets, evaluation practice, and deployment constraints. Three lessons stand out: generation must close the loop with analysis and verification or it drifts; grounding matters—use retrieval and tool context when semantics dominate, use physics priors when geometry and reliability rule; progress depends on shared artifacts—open interfaces, curated datasets with clear provenance, and benchmarks that align design and fab views. For practitioners, the path is pragmatic: start with narrow, high-value tasks, prefer small domain-tuned agents near the tools they drive, add physics where failure costs are high, and measure with published protocols.

Looking ahead, we expect tighter coupling of LLM agents with simulators and sign-off, standard schemas that carry intent from topology to masks, and benchmarks that score end-to-end quality, not only local gains. Smaller models that can be deployed locally within a design team’s own infrastructure, with well-documented training data and methodology, will speed adoption so that generation, grounding, and governance act together to shorten design cycles and raise yield.