Hardware Aspects of Machine Learning-Based Cardiac Fibrillation Diagnosis

1. Introduction

Atrial fibrillation (AF) is the most common sustained cardiac arrhythmia and a major contributor to adverse cardiovascular outcomes, including stroke, heart failure, and increased mortality [1]. Early detection and timely intervention are therefore critical to reduce the individual and societal burden associated with AF and related rhythm disorders. In recent years, the proliferation of wearable and portable electrocardiogram (ECG) devices and other Internet of Medical Things (IoMT) platforms has created an opportunity for continuous, out-of-clinic rhythm monitoring, but it has also raised important challenges regarding how to process and interpret large volumes of physiological data under strict constraints on energy, memory, cost, and connectivity [2,3].

Machine learning (ML) and deep learning (DL) methods have significantly improved the automatic analysis of ECG signals, achieving high performance in AF detection when combined with appropriate feature representations and evaluation protocols [4,5]. Edge-AI studies have demonstrated that AF classification can be executed on low-power embedded platforms, but they also highlight stringent limitations in on-device memory, compute, and energy budgets that often necessitate compact models and carefully optimised inference pipelines [6,7,8]. Purely cloud-based approaches, on the other hand, can exploit abundant computational resources but may introduce latency, bandwidth overhead, and privacy concerns that are undesirable for time-sensitive healthcare applications [2,3]. These considerations motivate hybrid architectures that distribute computation between resource-constrained edge nodes and cloud services in a task-aware manner.

On the classification side, compact deep neural networks operating on low-dimensional feature vectors provide a promising compromise between accuracy and deployability for AF detection on IoMT devices. In our earlier work, we proposed a Hjorth-parameter and DNN-based AF termination predictor on the Shandong Provincial Hospital Database (SPHD), achieving high diagnostic performance with inference executed on commercial microcontrollers and GPUs [9]. A follow-up ESP8266-based edge-to-cloud system demonstrated that Hjorth activity, mobility, and complexity computed in software on a low-cost microcontroller can support AF-related arrhythmia detection, with feature vectors transmitted to a cloud-hosted DNN classifier [10]. While these studies confirmed the suitability of Hjorth parameters and compact DNNs for embedded AF monitoring, they also revealed limitations in latency, energy efficiency, and scalability when feature extraction is implemented purely in software, particularly at higher sampling rates or in multi-channel wearable configurations.

To address these constraints, this work focuses on the hardware aspects of a Hjorth-parameter and DNN-based cardiac fibrillation diagnosis pipeline. We propose a fully synthesizable, parameterizable fixed-point hardware architecture for computing Hjorth activity, mobility, and complexity over ECG windows, together with a quantized neural network (QNN) that operates directly on the resulting fixed-point features. The hardware Hjorth module is designed as a reusable building block for embedded ECG processing pipelines, while the QNN is tailored to fit within the memory and computational envelope of an ESP8266-class edge node and to map efficiently onto a standard-cell ASIC flow. Using the same SPHD dataset and windowing protocol as in our previous work, we systematically evaluate the impact of fixed-point quantization on arrhythmia detection performance and report both algorithmic metrics (accuracy, F1-score, AUC) and hardware-oriented metrics (area, power, timing) obtained from synthesis in a 28 nm CMOS technology.

The main contributions of this paper are as follows:

• We propose a fully synthesizable, parameterizable hardware architecture for computing Hjorth activity, mobility, and complexity over ECG windows using fixed-point arithmetic, including derivative generation, accumulator banks, variance computation, and hardware divider and square-root units.
• We provide a systematic bit-width and scaling analysis for ECG signals in the millivolt range, deriving internal word lengths that prevent overflow while offering sufficient precision for subsequent classification.
• We design and implement a quantized DNN for cardiac fibrillation diagnosis that is compatible with the hardware Hjorth feature extractor.
• We present an experimental evaluation on a public AF dataset, comparing floating-point and quantized models, reporting algorithmic metrics (accuracy, F1-score, AUC) as well as hardware-oriented metrics (latency, area, and power), and discussing the trade-offs between performance, complexity, and deployability.

The remainder of the paper is organised as follows. Section 2 reviews related work on AF detection, Hjorth parameters, edge and IoMT architectures, model quantization for ECG analysis, and embedded hardware implementations. Section 3 details the fixed-point Hjorth hardware architecture and word-length design, while Section 4 presents the quantized neural network and its embedded and ASIC-oriented implementation. Section 5 reports experimental results and discusses the observed trade-offs, and Section 6 concludes the paper and outlines directions for future work.

2. Background and Related Work

2.1. Atrial Fibrillation Detection from ECG

AF detection has long relied on manual inspection of ECG recordings by trained clinicians, focusing on the absence of P waves, irregular RR intervals, and fibrillatory baseline activity. Recent advances in artificial intelligence (AI) have enabled automatic analysis of both single-lead and multi-lead ECG signals, leading to improved sensitivity and specificity for AF screening in ambulatory and wearable scenarios [1,11]. In particular, AI models applied to sinus-rhythm ECGs have shown the ability to detect patients at risk of paroxysmal or incident AF, broadening AF detection beyond episodes captured during overt arrhythmia [5,11]. Comprehensive recent reviews summarize how machine learning and deep learning approaches can support AF detection, risk stratification, and management across a variety of clinical and ambulatory settings [4,5].

A wide range of feature representations has been explored for AF detection, including time-domain descriptors, frequency-domain parameters, and morphology-based metrics derived from QRS complexes and atrial activity [4,9]. Traditional approaches often rely on heart-rate variability indices, P–R interval statistics, and spectral markers, whereas modern deep learning architectures can operate either on raw ECG segments, on time–frequency images, or on compact feature vectors [4,9]. Hjorth parameters constitute an attractive time-domain feature family because they capture signal variance, mobility, and complexity using low-order statistics and are therefore compatible with both classical machine learning models and lightweight embedded implementations [12].

2.2. Hjorth Parameters and Fixed-Point Implementations

Hjorth activity, mobility, and complexity were originally introduced as descriptors of stochastic processes and have since been widely applied to biomedical signals, including EEG and ECG, for classification and monitoring tasks [12]. For discrete-time signals, these parameters can be expressed in terms of the variance of the signal and the variance of its first and second discrete derivatives, making them amenable to running-sum implementations over finite windows [12]. This property is particularly appealing for resource-constrained hardware, because it allows the feature extractor to be realized using adders, subtractors, and accumulators, with divisions simplified by appropriate choices of window length.

Fixed-point realization of Hjorth parameters requires careful selection of the input format, internal word lengths, and scaling factors in order to avoid overflow and maintain sufficient numerical precision. In the context of ECG, where amplitudes are typically on the order of millivolts and derivatives can amplify noise, designers must dimension squared terms and accumulators to accommodate worst-case scenarios over the chosen window size. Parameterizable architectures that expose word-length and window-length parameters at synthesis time are therefore attractive, as they enable design-space exploration of the trade-offs between area, latency, and estimation accuracy in different application settings. Although prior work has investigated fixed-point implementations for generic biomedical feature extraction, there is still limited literature on fully synthesizable Hjorth hardware blocks tailored specifically to single-lead ECG monitoring on low-cost IoT platforms.

2.3. Edge and IoMT Architectures for Cardiac Monitoring

The proliferation of Internet of Medical Things (IoMT) platforms has motivated a variety of system architectures that distribute ECG acquisition, preprocessing, and analysis between edge devices, fog nodes, and cloud services [2,3]. Simple telemetry systems stream raw or lightly compressed ECG data to a remote server for offline or near real-time analysis, but such designs can incur high bandwidth consumption and may not scale well in large deployments [2,5]. More advanced solutions perform part of the processing pipeline on embedded microcontrollers or wearable devices, extracting compact feature vectors that are transmitted to an upstream backend, thereby reducing communication overhead and enabling local decision support [2,3].

Several recent works have specifically targeted AF detection on low-power microcontrollers and wearable platforms, proposing energy-efficient inference pipelines and compact models tailored to resource constraints [6,7,8]. For example, embedded-edge AF detectors based on heart-rate variability features and compact neural networks have demonstrated high accuracy while keeping energy per inference in the millijoule range, enabling long-term battery-powered screening [6]. Other studies have investigated real-time AF detection on wearable devices using lightweight models and heartbeat-interval features, confirming that clinically meaningful monitoring is feasible on severely resource-constrained hardware [7,8]. Hybrid fog–edge architectures further extend this idea by dynamically offloading computation between local and remote resources based on latency, reliability, and security requirements, offering a promising path toward scalable, resilient cardiac monitoring services in IoMT environments [3,5].

2.4. Model Compression and Quantization for ECG Analysis

Model compression techniques, such as pruning, weight sharing, and low-rank factorization, have been extensively investigated to reduce the computational and memory footprint of deep networks, including those applied to biomedical signals [4]. Among these techniques, fixed-point quantization has emerged as a particularly effective approach for embedded inference, where weights and activations are represented with reduced bit-widths while preserving most of the original model accuracy [8]. In the ECG domain, 8-bit and sub-8-bit quantized networks have been shown to maintain near-floating-point performance while significantly lowering memory usage and compute cost, enabling deployment on microcontroller-class devices and small-form-factor ECG recorders [6,8].

For AF detection specifically, quantized neural networks (QNNs) can be combined with compact feature representations, such as Hjorth parameters or heartbeat interval statistics, to minimize the overall resource requirements of the pipeline [6,7]. However, the interaction between feature quantization, internal word lengths in the preprocessing hardware, and the final classification performance remains an active area of research. Recent reviews emphasize that carefully co-designing signal representations, model architectures, and deployment platforms is crucial for translating AF AI models from proof-of-concept prototypes into robust, real-world monitoring systems [4,5].

2.5. Embedded and Hardware-Oriented Implementations

Beyond algorithmic advances, several works have examined embedded and hardware-oriented implementations of ECG and AF classifiers. Kachuee et al. [13] proposed a 1D CNN for arrhythmia classification on the MIT-BIH database, evaluated primarily on GPU, while Isin and Ozdalili [14] explored AlexNet-based transfer learning for ECG classification, also targeting GPU platforms. Oh et al. [15] combined convolutional and LSTM layers to capture temporal dependencies in ECG signals, achieving high accuracy on MIT-BIH but focusing on software inference. Hannun et al. [16] developed a deep ResNet for AF and arrhythmia detection on a large clinical dataset, demonstrating strong diagnostic performance but again relying on data-center–class hardware.

Quantisation-oriented studies have investigated reduced-precision deployments. Pu et al. [17] applied quantisation-aware training to binary CNNs for MIT-BIH arrhythmias, achieving near-floating-point accuracy in software. Ribeiro et al. [18] reported an INT8 post-training quantised 1D CNN running on an ARM Cortex-A55, with no accuracy loss relative to FP32. These works illustrate that low-bitwidth representations can preserve classification quality on general-purpose processors.

Closer to hardware accelerators, Chen et al. [19] realised a CNN-based classifier as an ASIC in a 180 nm CMOS technology, reporting 96.3% accuracy on MIT-BIH together with milliwatt-level power consumption. SparrowSNN [20] implemented a digital spiking neural network ASIC for arrhythmia detection, achieving 98.29% accuracy with microwatt-level power, while Rana et al. [21] mapped a related SNN architecture onto an iCE40 FPGA, reporting 98.4% accuracy and milliwatt-range power. The DARE Lab Inception-ResNeXt accelerator [22] targeted Cyclone-class FPGAs with quantised CNNs, achieving accuracies above 92% and up to 99.5% on MIT-BIH at hundreds of milliwatts of power.

Two recent works by the present authors form the immediate methodological precursors of this paper. Skrivanos et al. [9] introduced a Hjorth-parameter and DNN-based AF termination predictor on the SPHD database, achieving 94.8% accuracy and an AUC of 0.9479, with energy and latency evaluated on commercial 64-bit microcontrollers and a GPU. A follow-up PACET study [10] implemented an edge-to-cloud arrhythmia detection pipeline in which Hjorth features are computed on an ESP8266 node and classified by a cloud-hosted DNN, reaching 95% accuracy and AUC 0.95 on Shandong Provincial Hospital Database (SPHD) 1 while demonstrating feasibility on low-cost consumer hardware. Selected representatives of these software and hardware approaches, together with their reported performance and hardware metrics, are summarised in Table 3 and Table 4 and discussed further in Section 5. Despite this progress, there remains a lack of fully synthesised, low-power ASIC implementations that integrate both feature extraction and quantised inference in a modern CMOS standard-cell flow, which motivates the ASIC synthesis study presented subsequently.

3. Hardware Implementation of Hjorth Parameters

In our earlier ESP8266-based edge-to-cloud ECG monitoring system, the AD8232 analog front-end acquired single-lead ECG signals, and Hjorth activity, mobility, and complexity were computed in software on the microcontroller before transmission of feature vectors to a cloud-hosted deep neural network classifier [9,23]. This architecture demonstrated that low-complexity time-domain descriptors can support accurate AF-related arrhythmia detection on low-cost hardware, such as wearable or portable IoMT devices. However, implementing Hjorth parameters entirely in software imposed limitations on latency and energy efficiency, particularly as sampling rates increase or as the system is scaled from single-lead to multi-channel configurations (e.g., multi-lead chest patches, smartwatches with multiple sensing electrodes, or combined ECG–PPG wearable nodes). To address these constraints, the present work introduces a synthesizable fixed-point hardware block that computes Hjorth parameters in real time, providing a reusable building block for embedded ECG processing pipelines and quantized neural networks deployed in resource-constrained devices.

3.1. Discrete-Time Formulation

Let $x\left[n\right]$, $n=0,1,\dots ,N-1$, denote a discrete-time ECG segment within a window of length N samples. Following the classical Hjorth formulation, we define the first and second discrete derivatives as

$$d_1\left[n\right]=x\left[n\right]-x[n-1],n=1,\dots ,N-1,$$

$$d_2\left[n\right]=d_1\left[n\right]-d_1[n-1],n=2,\dots ,N-1.$$

The activity is proportional to the variance of the signal, the mobility is related to the ratio of the standard deviation of the first derivative to that of the signal, and the complexity is defined as the ratio of the mobility of the second derivative to the mobility of the first derivative [12]. In discrete-time notation, these parameters can be written as

$$\mathrm{Activity}={\sigma }_x^2=\mathbb{E}\left\{x^2\left[n\right]\right\}-{\mathbb{E}}^2\left\{x\left[n\right]\right\},$$

$$\mathrm{Mobility}=\sqrt{{\displaystyle \frac{{\sigma }_{d_1}^2}{{\sigma }_x^2}}},$$

$$\mathrm{Complexity}=\sqrt{{\displaystyle \frac{{\sigma }_{d_2}^2}{{\sigma }_{d_1}^2}}},$$

where ${\sigma }_x^2$, ${\sigma }_{d_1}^2$, and ${\sigma }_{d_2}^2$ denote the variances of $x\left[n\right]$, $d_1\left[n\right]$, and $d_2\left[n\right]$, respectively. In practice, expectations are estimated over the current window by computing running sums:

$${\mu }_x\approx {\displaystyle \frac{1}{N}}{\displaystyle \sum _{n=0}^{N-1}}x\left[n\right],{\mu }_{d_1}\approx {\displaystyle \frac{1}{N-1}}{\displaystyle \sum _{n=1}^{N-1}}{d}_1\left[n\right],{\mu }_{d_2}\approx {\displaystyle \frac{1}{N-2}}{\displaystyle \sum _{n=2}^{N-1}}{d}_2\left[n\right],$$

and similarly for second moments $\mathbb{E}\left\{x^2\left[n\right]\right\}$, $\mathbb{E}\left\{d_1^2\left[n\right]\right\}$, and $\mathbb{E}\left\{d_2^2\left[n\right]\right\}$. This structure naturally lends itself to a hardware implementation based on derivative generation and accumulator banks.

3.2. Fixed-Point Signal Representation

The proposed hardware block assumes a signed fixed-point input $x\left[n\right]$ of word length W bits, implemented in two’s complement. In the targeted ECG application, signal amplitudes are typically on the order of millivolts, with a dynamic range of approximately $0.5\mathrm{mV}-5\mathrm{mV}$ and additional headroom for artefacts [9]. To balance resolution and dynamic range, we adopt a Q-format with F fractional bits, for example a Q4.12 representation with $W=16$ and $F=12$, where one least significant bit corresponds to approximately $0.000244\mathrm{mV}$. An analog front-end and ADC produce samples proportional to the ECG voltage, and a simple digital scaling stage maps them into this fixed-point format before feeding the Hjorth module.

The window length is chosen as $N=2^k$ samples, so that divisions by N required for mean and second-moment estimation can be implemented as arithmetic right shifts by k bits in hardware. In the discrete-time Hjorth formulation, the variances and ratios formally involve normalisation by factors such as $N-1$ or $N-2$. However, in the proposed fixed-point implementation these denominators are approximated by N to preserve a shift-based realisation and avoid explicit division. For typical window lengths (e.g., $N=256$), the relative error introduced by this approximation is on the order of $1/N$ and was found to have negligible impact on the downstream classification performance in our experiments.

For example, with a window length of $N=256$, replacing the exact factors $1/(N-1)$ and $1/(N-2)$ by $1/N$ changes the scale by less than 0.4%. Concretely,

$${\displaystyle \frac{1}{255}}\approx 0.0039216,{\displaystyle \frac{1}{254}}\approx 0.0039370,{\displaystyle \frac{1}{256}}=0.00390625,$$

so the relative error of using $1/N$ instead of $1/(N-1)$ is

$${\displaystyle \frac{\frac{1}{256}-\frac{1}{255}}{\frac{1}{255}}}\approx -0.39\%,$$

and similarly $-0.78\%$ when approximating $1/(N-2)$ by $1/N$. These biases are well below the inherent variability of ECG-derived statistics and were observed to have negligible impact on the downstream classification metrics in our experiments. Furthermore, the corresponding scale factors ${\displaystyle \frac{N}{N-1}}$ and ${\displaystyle \frac{N}{N-2}}$ are absorbed into the subsequent neural network weights during training, allowing the Hjorth block to normalise all statistics by $N=2^k$ using simple shifts.

Figure 1. Block diagram of the fixed-point Hjorth parameter hardware: input, derivative, accumulation, statistics/variance, and mobility/complexity under FSM control.

Figure 1. Block diagram of the fixed-point Hjorth parameter hardware: input, derivative, accumulation, statistics/variance, and mobility/complexity under FSM control.

3.3. Derivative Generation Block

The first stage of the hardware architecture is a derivative generation block that produces $d_1\left[n\right]$ and $d_2\left[n\right]$ from the input sequence $x\left[n\right]$. A small delay line stores the previous samples $x[n-1]$ and $d_1[n-1]$, and each new input sample triggers the computation

$$d_1\left[n\right]=x\left[n\right]-x[n-1],$$

$$d_2\left[n\right]=d_1\left[n\right]-d_1[n-1].$$

Because subtraction of two W-bit values can increase the magnitude by approximately one bit, the derivative signals are allocated $D_X=W+2$ bits, providing one additional bit for the difference and an extra safety bit. This block consists only of registers and adders/subtractors, and thus can be synthesized efficiently in both FPGA and standard-cell ASIC flows.

3.4. Accumulator Bank and Statistics Computation

For each sample in the window, the architecture updates a set of accumulators that store sums and sums of squares of the signal and its derivatives:

$$S_x={\displaystyle \sum _{n=0}^{N-1}}x\left[n\right],S_{x^2}={\displaystyle \sum _{n=0}^{N-1}}{x}^2\left[n\right],$$

$$S_{d_1}={\displaystyle \sum _{n=1}^{N-1}}{d}_1\left[n\right],S_{d_1^2}={\displaystyle \sum _{n=1}^{N-1}}{d}_1^2\left[n\right],$$

$$S_{d_2}={\displaystyle \sum _{n=2}^{N-1}}{d}_2\left[n\right],S_{d_2^2}={\displaystyle \sum _{n=2}^{N-1}}{d}_2^2\left[n\right].$$

Squaring a $D_X$-bit value requires approximately $2D_X$ bits, so the multiplier outputs are dimensioned with $W_{\mathrm{SQ}}\approx 2D_X$ bits. Accumulating N samples can increase the required word length by ${log}_{2}N$ bits, therefore sum registers are chosen as

$$W_{\mathrm{SUM}}=W+{log}_{2}N+c_1,W_{\mathrm{SUMSQ}}=W_{\mathrm{SQ}}+{log}_{2}N+c_2,$$

where $c_1$ and $c_2$ are small safety margins that simplify synthesis and avoid overflow under worst-case ECG conditions. After N samples have been received, the statistics are updated by arithmetic right shifts:

$${\mu }_x=S_x\gg k,\mathbb{E}\left\{x^2\left[n\right]\right\}=S_{x^2}\gg k,$$

and similarly for $d_1\left[n\right]$ and $d_2\left[n\right]$. Variances are then computed as

$${\sigma }_x^2=max\left(0,\mathbb{E}\left\{x^2\left[n\right]\right\}-{\mu }_x^2\right),$$

$${\sigma }_{d_1}^2=max\left(0,\mathbb{E}\left\{d_1^2\left[n\right]\right\}-{\mu }_{d_1}^2\right),$$

$${\sigma }_{d_2}^2=max\left(0,\mathbb{E}\left\{d_2^2\left[n\right]\right\}-{\mu }_{d_2}^2\right),$$

with saturation at zero to avoid negative results due to finite precision. The activity output is directly assigned from ${\sigma }_x^2$, with suitable truncation or saturation to match the desired output word length.

3.5. Mobility and Complexity Engine

Mobility and complexity require ratios of variances and subsequent square-root operations:

$$r_{\mathrm{mob}}={\displaystyle \frac{{\sigma }_{d_1}^2}{{\sigma }_x^2}},r_{\mathrm{cpx}}={\displaystyle \frac{{\sigma }_{d_2}^2}{{\sigma }_{d_1}^2}},$$

$$\mathrm{Mobility}=\sqrt{r_{\mathrm{mob}}},\mathrm{Complexity}=\sqrt{r_{\mathrm{cpx}}}.$$

To implement these operations in a hardware-friendly manner, the proposed architecture uses digit-by-digit algorithms with a fixed number of clock cycles. The divider follows a restoring binary division scheme, which in each iteration compares the partial remainder to a shifted version of the divisor and updates the quotient bit accordingly. The integer square root is computed via a non-restoring method that processes two input bits per iteration and updates the partial root and remainder. Both algorithms require only shifts, additions, and comparisons, and are thus well suited to standard-cell synthesis or low-cost FPGA fabrics [24].

The divider inputs are dimensioned with $W_{\mathrm{DIV}}\approx 2W_{\mathrm{VAR}}$ bits, where $W_{\mathrm{VAR}}$ is the width of the variance registers, to accommodate products such as $2{\sigma }_{d_2}^2$ and $4{\sigma }_{d_1}^2$ without overflow. The exposed output width is set to $W_{\mathrm{OUT}}$ (for example, 24 bits), providing sufficient fixed-point resolution for the Hjorth parameters while limiting area and power consumption.

3.6. Control Finite State Machine and Handshaking

A finite state machine (FSM) orchestrates the accumulation and post-processing phases. During accumulation, the module accepts one sample per clock cycle while a window counter is incremented. When N samples have been received, the FSM freezes the input interface, computes the statistics and Hjorth parameters, asserts a valid flag for the output vector, and finally resets the accumulators to start the next window. The interface exposes standard ready/valid handshaking signals to facilitate integration with upstream ADC or ESP8266-based acquisition modules and downstream classifiers.

4. Quantized Neural Network for Cardiac Fibrillation Diagnosis

4.1. Baseline Deep Neural Network and Dataset

In earlier work on AF-related heart disease detection, Hjorth parameters computed from single-lead ECG windows were used as inputs to a compact deep neural network (DNN) that achieved high diagnostic performance on the Shandong Provincial Hospital Database (SPHD) [9]. The baseline model is a feedforward multilayer perceptron with rectified linear unit (ReLU) activations, dropout regularisation, and a final sigmoid output, trained in floating-point arithmetic using standard optimisation techniques. The same dataset and 1-minute windowing protocol are adopted in this extended study to ensure a fair comparison between the floating-point reference and the fixed-point implementations [9].

The classifier operates on a three-dimensional feature vector comprising Hjorth activity, mobility, and complexity, and retains exactly the same multilayer perceptron topology as in the AF-termination predictor [9] and the ESP8266-based edge-to-cloud AF-termination predictor [10]. In brief, the network consists of 9 fully connected hidden layers with ReLU activations and dropout, followed by a single-output neuron that produces a scalar decision score. In the present work, only the numerical representation and deployment platform are modified: the floating-point weights and activations used in [9,10] are replaced by 10–12-bit fixed-point formats, and the network is realised as a synthesised datapath in which all constant multipliers are implemented using multiple constant multiplication.

For each ECG recording, fixed-length windows of 1 minute are segmented and represented by the three Hjorth descriptors, extracted either in software (in previous studies) or, in this work, by the proposed fixed-point hardware block. The resulting feature vectors are labelled according to the AF-related outcome of interest and used to train and evaluate binary classifiers. The original floating-point DNN thus serves as a consistent reference model against which the impact of fixed-point quantisation on arrhythmia detection performance can be systematically assessed.

4.2. Quantization Strategy

The baseline DNN is converted into a quantized neural network (QNN) with reduced-precision weights and activations. Recent studies on embedded AF detection and ECG edge-AI have demonstrated that 8-bit fixed-point representations can preserve most of the predictive power of floating-point models while substantially reducing memory footprint and computational cost [6,8]. Motivated by these findings, we adopt a uniform symmetric quantization scheme in which each layer’s weights and activations are mapped from floating point to signed 10 to 12-bit integers using learned or analytically derived scale factors.

The Hjorth feature vectors produced by the hardware block are first normalized to a fixed dynamic range compatible with the quantized network’s input layer. Internally, the QNN performs integer matrix–vector operations followed by fixed-point accumulation, and non-linearities are approximated using piecewise-linear or lookup-table-based implementations where necessary. Quantization-aware training is used to reduce the accuracy gap between the floating-point and quantized models, with simulated quantization applied during the forward pass and straight-through estimators during backpropagation. This procedure has been shown to limit performance degradation in medical time-series applications, including AF detection and broader ECG abnormality classification [4,8].

4.3. Accuracy and Robustness Evaluation

The performance of the quantized DNN is evaluated on the same SPHD-based dataset and train–test split as the floating-point baseline, using accuracy, F1-score, and area under the ROC curve (AUC) as metrics [9]. Consistent with prior work on quantized ECG models, the 8-bit QNN achieves accuracy and AUC values close to those of the floating-point network, with only a minor reduction that falls within typical variability across training runs [6,8]. Confusion matrices and ROC curves are analyzed to assess the sensitivity and specificity trade-offs and to verify that quantization does not disproportionately affect performance in clinically critical operating regions.

Robustness is further examined by studying the impact of quantization on different patient subgroups and signal conditions, leveraging insights from recent reviews on AI in AF detection and management [4,5]. These analyses support the conclusion that, when combined with the fixed-point Hjorth feature extractor, the quantized DNN provides a practical balance between algorithmic performance and resource efficiency, making it suitable for deployment in low-cost IoT cardiac monitoring nodes and wearable devices.

4.4. Effect of Quantization on ROC Curves and Confusion Matrices

Figure 2 and Figure 3 together with Table 1 summarize the impact of the end-to-end fixed-point word-length on the detection performance of the proposed system. The ROC curves compare the floating-point baseline against the fully quantized hardware pipeline for each bit-width, while the confusion matrices report the corresponding operating point at the default decision threshold.

At very low precision (6 bits), the ROC curve of the hardware pipeline departs substantially from the floating-point baseline, with a markedly lower true-positive rate (TPR) for a given false-positive rate (FPR) across most of the operating range. This is reflected in the numerical metrics, where the 6-bit configuration attains an AUC of 0.8969 and an accuracy of 77.71%, but also exhibits a high number of false negatives (FN = 83, TP = 160), meaning that a large fraction of AF-related windows are missed. Increasing the word-length to 8 bits improves both AUC and accuracy (0.9420 and 87.71%, respectively), yet the ROC curve still shows a visible gap to the baseline in the low-FPR region, and the false-negative count (FN = 30) remains significantly higher than in the higher-precision configurations.

In contrast, for word-lengths of 10 bits and above, the quantized ROC curves almost entirely overlap with the floating-point reference. The 10-bit configuration achieves an AUC of 0.9704 and an accuracy of 93.75%, with only 11 false negatives and 19 false positives (TN = 218, FP = 19, FN = 11, TP = 232). The 12-bit pipeline exhibits very similar behaviour (AUC = 0.9712, accuracy = 93.75%), with a slightly different trade-off between false positives and false negatives (TN = 219, FP = 18, FN = 12, TP = 231), confirming that quantization noise at this precision has negligible impact on the sensitivity–specificity balance. The 14-bit configuration further increases AUC to 0.9885 while maintaining an accuracy of 93.54% and the same number of false negatives as the 12-bit case, indicating that additional bits mainly provide a marginal gain in the extreme tail of the ROC curve.

Interestingly, further increasing the precision to 16 bits does not yield measurable gains over the 12–14-bit range. The 16-bit pipeline reaches the same AUC as the floating-point model (0.9714 in the plotted operating regime), but achieves an accuracy of 93.54%, with error counts (TN = 218, FP = 19, FN = 12, TP = 231) that are effectively indistinguishable from those of the 14-bit configuration. This suggests that, beyond approximately 12 bits, numerical precision is no longer the limiting factor for classification performance, and that small differences in accuracy are dominated by threshold calibration and dataset variability rather than quantization error.

Overall, the combined ROC and confusion-matrix analysis indicates that a fixed-point implementation with 10–12 bits provides a favourable trade-off between hardware cost and diagnostic performance. At these precisions, the end-to-end quantized pipeline closely matches the floating-point baseline in terms of AUC and maintains a low false-negative rate, while substantially reducing memory footprint and arithmetic complexity compared to higher word-lengths and avoiding the severe performance degradation observed at 6–8 bits.

It is worth noting that the 16-bit configuration does not outperform the 10–12-bit designs, despite offering higher nominal precision. The ROC curves show that the 16-bit pipeline attains virtually the same AUC as the floating-point baseline, indicating that its ability to rank positive and negative examples is not degraded. The slightly lower accuracy observed in Table 1 arises at the specific operating threshold used for all models and is attributable to small calibration differences and finite-sample variability, rather than to a lack of numerical precision. In practice, re-tuning the decision threshold for the 16-bit model yields confusion matrices that are statistically indistinguishable from those of the 10–12-bit configurations, confirming that additional bits beyond approximately 12 do not provide meaningful gains in classification performance for this task.

4.5. Hardware Architecture of the Quantized Neural Network

Figure 4 illustrates the top-level hardware architecture that integrates the fixed-point Hjorth parameter extractor with the quantized neural network classifier. At the input, a single-lead ECG signal is sampled by the front-end and presented to the Hjorth block as a stream of fixed-point samples together with a valid signal (signal_in, in_valid). The Hjorth module performs windowed processing and outputs the three time-domain descriptors activity, mobility, and complexity once per window, accompanied by an out_valid handshake signal. The in_ready signal allows backpressure towards the upstream acquisition logic, ensuring that new samples are accepted only when the Hjorth block is ready to process them.

The Hjorth outputs are captured by a small register interface that decouples the feature-extraction and classification stages. This register bank stores the three Hjorth parameters (in1, in2, in3) in the fixed-point format expected by the neural network and asserts a start control signal when a new feature vector is available. The register interface also monitors the busy flag from the neural network engine and refrains from launching a new evaluation until the previous inference has completed, thereby providing a simple yet robust handshake between the two blocks.

The quantized neural network is realized as the hardware_fcn block described in Section 4, which implements a feedforward multilayer perceptron with fixed-point weights, biases, and activations. Internally, the network iterates over layers, neurons, and inputs under the control of a finite-state machine, accumulating multiply–accumulate (MAC) results in wider fixed-point registers before applying the neuron nonlinearity. The three Hjorth parameters in1, in2, and in3 serve as the input vector of the first layer, and the final layer produces an 8-bit decision score out1 together with a valid signal enout, which are forwarded to the top-level classification output block.

To reduce hardware complexity, all multiplications by network weights are implemented using multiple constant multiplication (MCM) rather than generic multipliers. Specifically, the constant-coefficient multiplications in the MAC datapath are synthesized as shift-and-add networks optimized using the approach of García and Volkova [25]. In our flow, the quantized weight matrices are first exported from the training framework and then processed by the Simurg toolchain to generate synthesizable Verilog, which is subsequently synthesized and analysed using a commercial standard-cell CAD tool (Cadence Genus) targeting a 28 nm CMOS technology. The resulting netlist forms the basis of the atrial_detector block diagram shown in Figure 5, and the reported area–power–timing figures in Section 5 are obtained from this same synthesis setup.

5. Experimental Results

5.1. Classification Summary

The effect of fixed-point quantization on the end-to-end classification performance is analysed in detail in Section 4.4, where confusion matrices, ROC curves, and aggregate metrics for 6–16 bit configurations are reported and compared against the floating-point baseline. In brief, the 6-bit and 8-bit implementations exhibit a pronounced degradation in accuracy and AUC due to a significant increase in false negatives, which renders them unsuitable for reliable AF-related screening. By contrast, the 10-bit and 12-bit pipelines achieve accuracies around 93.7% and AUC values above 0.97, with confusion matrices that differ from the floating-point reference by only a few misclassified windows, indicating that quantization noise at these precisions has negligible effect on the sensitivity–specificity trade-off.

Higher precisions (14 and 16 bits) do not provide meaningful gains over the 10–12-bit designs. Small variations in AUC and error counts fall within the expected range of calibration differences and finite-sample variability and mainly reflect the use of a common decision threshold across all implementations. Overall, the classification results support a 10–12-bit fixed-point representation as a practical compromise between numerical robustness and implementation complexity.

5.2. ASIC Synthesis Results in a 28 nm Standard-Cell Library

To quantify the hardware cost of the proposed architecture, the atrial_detector—comprising the Hjorth feature extractor, register interface, and quantized neural network engine—was synthesised to a 28 $\mathrm{n}$$\mathrm{m}$ CMOS standard-cell library at the typical process corner. Two timing constraints were applied for each of the two Pareto-optimal fixed-point word-lengths (10 bit and 12 bit): a fast target, which maximises operating frequency, and a relaxed target, which allows the synthesis tool to trade timing margin for power and area reduction. The resulting post-synthesis delay, area, and power figures are summarised in Table 2, while the corresponding area–delay and power–delay trends are illustrated in Figure 6.

Several observations follow from Table 2. First, the fast timing constraint yields a critical-path delay of 7084 $\mathrm{p}$$\mathrm{s}$ for both word-lengths, corresponding to a maximum clock frequency of approximately 141 $\mathrm{M}$$\mathrm{Hz}$. Relaxing the timing target to 8154 $\mathrm{p}$$\mathrm{s}$– 8155 $\mathrm{p}$$\mathrm{s}$ allows the synthesis tool to choose smaller drive-strength cells, reducing power from $3.062$ $\mathrm{m}$$\mathrm{W}$ to $2.627$ $\mathrm{m}$$\mathrm{W}$ for the 10-bit design and from $3.126$ $\mathrm{m}$$\mathrm{W}$ to $2.682$ $\mathrm{m}$$\mathrm{W}$ for the 12-bit design, with only a modest increase in delay. Second, increasing the precision from 10 bit to 12 bit results in a modest area overhead: the fast configurations differ by approximately 797 $\mu$m² (about 4%), confirming that the multiplierless MCM datapath scales efficiently with word-length. The power difference between the 10-bit and 12-bit relaxed configurations is similarly small (around 2%), indicating that the 12-bit design remains competitive when a slightly higher numerical precision is desired.

Table 3 summarises representative embedded and hardware AF/ECG classifiers. Existing microcontroller-based solutions typically employ 8-bit or sub-8-bit quantised models and report accuracies above 95% on various public datasets while operating in the milliwatt range. Direct numerical comparison is complicated by differences in datasets and evaluation protocols, but the proposed detector is broadly aligned with this literature in terms of algorithmic performance while providing a distinct contribution on the hardware side: a fully synthesised fixed-point pipeline, including a Hjorth feature extractor and a multiplierless quantised neural network, implemented in a 28 nm standard-cell flow with area around $2.0\times {10}^4\mu {\mathrm{m}}^2$ and power below 3.2 mW. This combination makes the design suitable as a hardened core for future IoMT ECG monitoring nodes.

Table 3. Comparison with selected ECG/AF classifiers and hardware implementations.

Reference	Task / Dataset	Model / Prec.	Platform	Acc.(%)/AUC
Kachuee et al. [13]	MIT-BIH∗	1D CNN, FP32	GPU	93.4/-
Isin & Ozdalili [14]	MIT-BIH	AlexNet (transfer), FP32	GPU	92.0/-
Oh et al. [15]	MIT-BIH	CNN+LSTM, FP32	GPU	98.1/-
Hannun et al. [16]	AF / custom	34-layer ResNet, FP32	GPU	-/0.978
Pu et al. [17]	MIT-BIH	Binary CNN (QAT)	SW	96.9/-
Ribeiro et al. [18]	MIT-BIH	1D CNN, INT8 (PTQ)	ARM Cortex	99.6/-
Chen et al. [19]	hMIT-BIH	CNN ASIC, fixed-point	ASIC, 180 nm	96.3/-
SparrowSNN [20]	MIT-BIH	Digital SNN	ASIC	98.3/-
Rana et al. [21]	MIT-BIH	SNN FPGA	iCE40 FPGA	98.4/-
Wang et al. [26]	[27]	CNN FPGA	Cyclone V	92.9/-
Skrivanos et al. [9]	AF (SPHD)	Hjorth + DNN, FP32	GPU / MCUs	94.8/0.948
Skrivanos et al. [10]	AF (SPHD)	Hjorth + DNN, FP32	ESP8266 + cloud	95/0.95
This work	AF (SPHD)	Hjorth + DNN, 10–12-bit	ASIC, 28 nm	93.7/>0.97

* The data are publicly available at: https://www.kaggle.com/datasets/mondejar/mitbih-database

Table 3. Comparison with selected ECG/AF classifiers and hardware implementations.

Reference	Task / Dataset	Model / Prec.	Platform	Acc.(%)/AUC
Kachuee et al. [13]	MIT-BIH∗	1D CNN, FP32	GPU	93.4/-
Isin & Ozdalili [14]	MIT-BIH	AlexNet (transfer), FP32	GPU	92.0/-
Oh et al. [15]	MIT-BIH	CNN+LSTM, FP32	GPU	98.1/-
Hannun et al. [16]	AF / custom	34-layer ResNet, FP32	GPU	-/0.978
Pu et al. [17]	MIT-BIH	Binary CNN (QAT)	SW	96.9/-
Ribeiro et al. [18]	MIT-BIH	1D CNN, INT8 (PTQ)	ARM Cortex	99.6/-
Chen et al. [19]	hMIT-BIH	CNN ASIC, fixed-point	ASIC, 180 nm	96.3/-
SparrowSNN [20]	MIT-BIH	Digital SNN	ASIC	98.3/-
Rana et al. [21]	MIT-BIH	SNN FPGA	iCE40 FPGA	98.4/-
Wang et al. [26]	[27]	CNN FPGA	Cyclone V	92.9/-
Skrivanos et al. [9]	AF (SPHD)	Hjorth + DNN, FP32	GPU / MCUs	94.8/0.948
Skrivanos et al. [10]	AF (SPHD)	Hjorth + DNN, FP32	ESP8266 + cloud	95/0.95
This work	AF (SPHD)	Hjorth + DNN, 10–12-bit	ASIC, 28 nm	93.7/>0.97

* The data are publicly available at: https://www.kaggle.com/datasets/mondejar/mitbih-database

Table 4. Reported hardware metrics for selected ECG/AF implementations.

Reference	Platform	Power	Latency / Energy
DARE Lab [22]	FPGA (Cyclone)	200 mW	2.52 ms / 76.7 µJ
Chen et al. [19]	ASIC, 180 nm	4.4 mW	–
SparrowSNN [20]	ASIC (digital SNN)	6.1 µW	5.44 ms / 31.39 nJ
Rana et al. [21]	FPGA (iCE40)	11.8 mW	4.32 ms / 50.98 µJ
Wang et al. [26]	FPGA (Cyclone V)	67.74 mW	–
Skrivanos et al. [9] (MCU A)	64-bit MCU A	1340 mW	550 ms / inference
Skrivanos et al. [9] (MCU B)	64-bit MCU B	198 mW	194 ms / inference
Skrivanos et al. [9] (GPU)	Discrete GPU	300 mW	0.96 ms / inference
This work (10-bit)	ASIC, 28 nm	3.06 mW	7.08 ns (crit. path)
This work (12-bit)	ASIC, 28 nm	3.13 mW	7.08 ns (crit. path)

Table 4. Reported hardware metrics for selected ECG/AF implementations.

Reference	Platform	Power	Latency / Energy
DARE Lab [22]	FPGA (Cyclone)	200 mW	2.52 ms / 76.7 µJ
Chen et al. [19]	ASIC, 180 nm	4.4 mW	–
SparrowSNN [20]	ASIC (digital SNN)	6.1 µW	5.44 ms / 31.39 nJ
Rana et al. [21]	FPGA (iCE40)	11.8 mW	4.32 ms / 50.98 µJ
Wang et al. [26]	FPGA (Cyclone V)	67.74 mW	–
Skrivanos et al. [9] (MCU A)	64-bit MCU A	1340 mW	550 ms / inference
Skrivanos et al. [9] (MCU B)	64-bit MCU B	198 mW	194 ms / inference
Skrivanos et al. [9] (GPU)	Discrete GPU	300 mW	0.96 ms / inference
This work (10-bit)	ASIC, 28 nm	3.06 mW	7.08 ns (crit. path)
This work (12-bit)	ASIC, 28 nm	3.13 mW	7.08 ns (crit. path)

6. Conclusions and Future Work

This paper presented a fixed-point hardware architecture for real-time cardiac fibrillation diagnosis that combines Hjorth parameter extraction with a quantised neural network, targeting low-power embedded and IoMT applications. The proposed pipeline was evaluated on the SPHD database using 1-minute ECG windows, showing that 10–12 bit fixed-point implementations can match the diagnostic performance of the floating-point baseline (accuracy around 93.75%, AUC above 0.97) while significantly reducing implementation cost. ASIC synthesis results in a 28 $\mathrm{n}$$\mathrm{m}$ standard-cell library demonstrated that the complete atrial_detector core fits within approximately $2.0\times {10}^4\mu {\mathrm{m}}^2$ and operates in the $2.6$ $\mathrm{m}$$\mathrm{W}$– $3.2$ $\mathrm{m}$$\mathrm{W}$ power range, confirming its suitability for wearable and IoT ECG monitoring nodes.

Building on two previous Hjorth- and DNN-based pipelines for AF termination prediction and ESP8266-based edge-to-cloud arrhythmia detection, the present work moves the entire feature-extraction and inference chain into a fully synthesised, multiplierless ASIC flow. This design achieves a favourable balance between algorithmic performance, area, and power compared with existing FPGA and ASIC ECG classifiers, while offering a reusable core that can be integrated into broader IoMT platforms.

Future work will extend this study along several directions. First, cross-dataset evaluation on additional benchmarks (e.g., MIT-BIH and PhysioNet Challenge datasets) and multi-class rhythm classification will be pursued to assess generalisation beyond the binary AF task considered here. Second, full physical implementation, including place-and-route, post-layout timing closure, and sign-off power analysis, will be performed to validate the pre-layout synthesis results and to explore further area and energy optimisations. Third, mixed-precision schemes in which only selected layers or weight tensors are kept at 12 bits while others are reduced to 8 bits will be investigated as a means to lower power without sacrificing the accuracy ceiling identified in this work. Finally, integration with complete IoMT prototypes, combining the proposed ASIC with wireless front-ends and energy-harvesting subsystems, will be explored to demonstrate end-to-end operation in realistic wearable and remote-monitoring scenarios.