Submitted:
01 July 2026
Posted:
02 July 2026
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Abstract
Keywords:
1. Introduction
- (a)
- Electronic Feature detection to identify and tag certain data that is of interest to the application by electronic means only, e.g., filtering.
- (b)
- Storage switching mechanism to enable swapping data between two processors with a multiplexer for decision-making at specific time periods. This reduces the time during which power consumption is high.
2. Related Work
2.1. Edge Computations and Architectures
2.1.1. Edge AI
- Reduced Data Transmission: Processing data locally minimizes the need to send large volumes of data to centralized servers, thereby saving energy.
- Lower Latency and Bandwidth Usage: Edge AI enables real-time decision-making without relying on constant cloud connectivity, reducing network strain and associated energy costs.
- Scalability: Efficient edge AI solutions can be scaled across numerous devices without proportionally increasing energy consumption, making them ideal for widespread deployment in industrial applications.
2.1.2. Multiple Processors in Edge
2.2. Edge Power Consumption
2.3. Electronics Filtering
3. Proposed Dual-Processor Architecture
- a)
- capture data in real time as part of monitoring
- b)
- Detect events or patterns in the data based on a known set of target patterns or classes
- c)
- Send the list of events to users.
3.1. Cost of Classification
3.1.1. Measuring Time and Power Consumption
3.1.2. Minimum Segment Size
- Assuming that the time gap between each classification bout is δ (which could be in hours), the total cost of a decision for each classification bout would depend on the entire recording period. The net time to process this would be lower than the continuous processing every few milliseconds.
- A cold start problem arises from the need to determine where to start looking, even if the processing time is lower than the time required for data collection. The classifier requires information on where to begin searching for the target pattern. Without this, the scheduler would have to iterate through all the collected information frame by frame or segment by segment. If additional feature information is recorded, then the segments can be tagged, and the clusters T can be formed accordingly.
3.2. Non-Real-Time Edge Classification Architecture
- Data Accumulations with Augmentation: Raw data can easily be accumulated by the collector. But suppose the classifier processes all of that data without any supporting information. In that case, the net time and power consumption will still be unnecessarily high, even if the classification time for each segment is significantly shorter.
- Storage Hand-Over: When enough data is accumulated in the shared storage, the collector hands it over to the classifier. This process requires a clean mechanism and supports the required speed and throughput.
- Inference: The secondary classifier processor has significantly more storage available to it. When running the classification algorithm, it can use advanced libraries such as TensorFlow Lite. This would allow it to load multiple models to classify the raw data. The choice of model can be driven by several factors, such as the time of day or additional information collected during the first phase. The ability to invoke multiple models tailored to specific situations on the device enables it to identify multiple target patterns. The decision of which models to use can also be made externally and communicated to the device.
3.2.1. Supplementary Information to the Input Signal
- extended periods () of low non-zero voltage when there is a massive change or burst in the sound level. The RC values can determine the duration of this, depending on the sound environment. This has to be monitored by a dedicated timer on the collector microcontroller. This is a suitable arrangement, as the AUG, while reliable, would have a very low voltage (<500 mV or even <10 mV), which is difficult to detect as a proper interrupt and thus must be polled. This is better for saving power.
- short bursts of HIGH or LOW, which can be attached to a dedicated interrupt. However, for this, an additional layer of amplification is required on the AUG to detect the change at the pin. This should result in an additional power drain and is not suitable for power savings.
3.2.2. Memory Exchange Between Processors
| Line | From | To | Description |
|---|---|---|---|
| IPWR | Collector | Classifier (Power) | This line allows the Collector to enable or disable the classifier’s power input. |
| FIN | Classifier | Collector | This is an input to the Collector that informs it when the Classifier has finished classification. |
| CSW | Collector | MUX | This line enables the Collector to switch the SPI lines connected to the MUX mechanism between the Collector and the classifier. |
3.2.3. Decisions by Classifier Processor
4. Tests and Results
4.1. Electronic Feature Detection
- Detection rate: This indicates whether the EFD reliably detects a target sound as soon as it occurs. We test this with two sound levels from a PC speaker. The amplitude threshold was set to 50mV for this configuration.
4.2. Accuracy of Classification Compared to Power Savings
4.2.1. Training the AI Model


4.2.2. Results: Accuracy of Classification
4.2.3. Results: Cost of Inference
4.2.4. Power Characteristics
5. Discussions
5.1. Limitations and Future Work
- (a)
- environmental conditions as determined by additional onboard sensors. For example, it’s a rainy day or a sunny day.
- (b)
- External communication and changing the settings through remote control
- (c)
- Time factors, e.g., time of day, day in calendar, time elapsed since any known event has passed.
5.2. Key Advantages of the Multi-Processor Architecture
- (a)
- Prototyping: A key advantage of the architecture is the removal of the size limits of the AI models. It is often a tedious process to create an AI model that is both accurate and small enough to fit in devices’ memory. Also, it is most often just one model on a single processor. In the proposed architecture, multiple models can be loaded and selected according to a controlled strategy. This is very useful during the prototyping phases of development, where the device can first be tested for practicality in the target environment, allowing the AI models to be further optimized at a later stage.
- (b)
- Scalability: We discussed a dual-processor mechanism in this paper and considered only one kind of data. It can be scaled to include 1 or 2 storage devices being switched among multiple processors. Only the processor would collect the data, while the others would run classification individually. This would allow for parallel classifications. The proposed scheme would be effective as long as the total length of segments from the start of the last classification round (δ), or the sum of all segment lengths of the current Ω, is less than or more than the product of the number of processors (n), the number of segments in Ω, and the average inference time, i.e.,
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Abbreviations
| EFD | Electronics Feature Detection |
| NRTC | Non-Real-Time Classification |
References
- Shi, W.; Cao, J.; Zhang, Q.; Li, Y.; Xu, L. Edge Computing: Vision and Challenges. IEEE Internet Things J. 2016, 3, 637–646. [Google Scholar] [CrossRef]
- Chen, J.; Ran, X. Deep Learning With Edge Computing: A Review. Proc. IEEE 2019, 107, 1655–1674. [Google Scholar] [CrossRef]
- Han, S.; Pool, J.; Tran, J.; Dally, W. Learning both weights and connections for efficient neural network. Adv. Neural Inf. Process. Syst. 2015, 28. [Google Scholar]
- Teixeira, R.C.M.; Carvalho, C.B.; Calafate, C.T.; Mota, E.; Fernandes, R.A.; Printes, A.L.; Nascimento, L.B.F. FloatingBlue: A Delay Tolerant Networks-Enabled Internet of Things Architecture for Remote Areas Combining Data Mules and Low Power Communications. Sensors 2024, 24. [Google Scholar] [CrossRef] [PubMed]
- Madamori, O.; Max-Onakpoya, E.; Erhardt, G.D.; Baker, C.E. Enabling Opportunistic Low-cost Smart Cities By Using Tactical Edge Node Placement. Proceedings of the 2021 16th Annual Conference on Wireless On-demand Network Systems and Services Conference (WONS) 2021, 2021, 1–8. [Google Scholar] [CrossRef]
- David, R.; Duke, J.; Jain, A.; Janapa Reddi, V.; Jeffries, N.; Li, J.; Kreeger, N.; Nappier, I.; Natraj, M.; Wang, T. Tensorflow lite micro: Embedded machine learning for tinyml systems. Proc. Mach. Learn. Syst. 2021, 3, 800–811. [Google Scholar]
- Hymel, S.; Banbury, C.R.; Situnayake, D.; Elium, A.; Ward, C.; Kelcey, M.; Baaijens, M.; Majchrzycki, M.; Plunkett, J.; Tischler, D.; et al. Edge Impulse: An MLOps Platform for Tiny Machine Learning. ArXiv 2022, abs/2212.03332. [Google Scholar]
- Lai, L.; Suda, N.; Chandra, V. CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs. 2018. [Google Scholar] [PubMed]
- Warden, P.; Situnayake, D. TinyML: Machine Learning with TensorFlow Lite on Arduino and Ultra-low-power Microcontrollers; O’Reilly, 2020. [Google Scholar]
- Jacob, B.; Kligys, S.; Chen, B.; Zhu, M.; Tang, M.; Howard, A.; Adam, H.; Kalenichenko, D. Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference. In Proceedings of the 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 18-23 June 2018, 2018; pp. 2704–2713. [Google Scholar]
- Han, S.; Pool, J.; Tran, J.; Dally, W.J. Learning both weights and connections for efficient neural networks. In Proceedings of the Proceedings of the 29th International Conference on Neural Information Processing Systems -, Montreal, Canada, 2015; Volume 1, pp. 1135–1143. [Google Scholar]
- Hinton, G.E.; Vinyals, O.; Dean, J. Distilling the Knowledge in a Neural Network. ArXiv 2015, abs/1503.02531. [Google Scholar]
- Banbury, C.; Zhou, C.; Fedorov, I.; Matas, R.; Thakker, U.; Gope, D.; Janapa Reddi, V.; Mattina, M.; Whatmough, P. Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers. Proc. Mach. Learn. Syst. 2021, 3, 517–532. [Google Scholar]
- Cerutti, G.; Prasad, R.; Brutti, A.; Farella, E. Compact recurrent neural networks for acoustic event detection on low-energy low-complexity platforms. IEEE J. Sel. Top. Signal Process. 2020, 14, 654–664. [Google Scholar]
- Prince, P.; Hill, A.; Piña Covarrubias, E.; Doncaster, P.; Snaddon, J.L.; Rogers, A. Deploying Acoustic Detection Algorithms on Low-Cost, Open-Source Acoustic Sensors for Environmental Monitoring. Sensors 2019, 19, 553. [Google Scholar] [CrossRef] [PubMed]
- Miquel, J.; Latorre, L.; Chamaillé-Jammes, S. Energy-Efficient Audio Processing at the Edge for Biologging Applications. J. Low. Power Electron. Appl. 2023, 13, 30. [Google Scholar] [CrossRef]
- Jean, D.; Turner, J.; Hedgecock, W.; Kalmár, G.; Wittemyer, G.; Lédeczi, Á. Animal-Borne Adaptive Acoustic Monitoring. J. Sens. Actuator Netw. 2025, 14, 66. [Google Scholar] [CrossRef]
- Sad, C.; Kampelopoulos, D.; Sofianidis, I.; Kanelis, D.; Nikolaidis, S.; Tananaki, C.; Siozios, K. Deep Edge IoT for Acoustic Detection of Queenless Beehives. Electronics 2025, 14, 2959. [Google Scholar] [CrossRef]
- Krishna, A.; Lee, W.-J. Influ. Duty-Cycle Rec. Meas. Bat Act. Passiv. Acoust. Monit. 2025. [CrossRef]
- Georgiev, P.; Lane, N.D.; Rachuri, K.K.; Mascolo, C. Dsp. ear: Leveraging co-processor support for continuous audio sensing on smartphones. In Proceedings of the Proceedings of the 12th ACM Conference on Embedded Network Sensor Systems, 2014; pp. 295–309. [Google Scholar]
- Oletic, D.; Bilas, V.; Magno, M.; Felber, N.; Benini, L. Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up. In Proceedings of the Proceedings of the 2016 Conference on Design, Automation & Test in Europe, Dresden, Germany, 2016; pp. 355–360. [Google Scholar]
- Gazivoda, M.; Oletić, D.; Bilas, V. Features and Always-On Wake-Up Detectors for Sparse Acoustic Event Detection. Electronics 2022, 11, 478. [Google Scholar] [CrossRef]
- Fromm, R.; Kanoun, O.; Derbel, F. Wake-Up Receivers Based on Commercial Off-the-Shelf Components: A Survey. IEEE J. Microwaves 2026, 6, 42–80. [Google Scholar] [CrossRef]
- Byers, C. Heterogeneous Computing in the Edge. Ind. Internet Consort. 2021. [Google Scholar]
- Zao, J.; Byers, C.; Murphy, B.; AbiEzzi, S.; Banks, D.; An, K.; Michaud, F.; Bartfai-Walcott, K. The industrial internet of things distributed computing in the edge; 2020. [Google Scholar]
- Li, P.; Wang, X.; Huang, K.; Huang, Y.; Li, S.; Iqbal, M. Multi-Model Running Latency Optimization in an Edge Computing Paradigm. Sensors 2022, 22, 6097. [Google Scholar] [CrossRef] [PubMed]
- Hu, F.; Mehta, K.; Mishra, S.; AlMutawa, M. Distributed Edge AI Systems. In Proceedings of the Proceedings of the 16th IEEE/ACM International Conference on Utility and Cloud Computing, Taormina (Messina), Italy, 2024; p. Article 56. [Google Scholar]
- Liu, Y.; Qu, H.; Chen, S.; Feng, X. Energy efficient task scheduling for heterogeneous multicore processors in edge computing. Sci. Rep. 2025, 15, 11819. [Google Scholar] [CrossRef] [PubMed]
- Taneja, J.; Jeong, J.; Culler, D. Design, Modeling, and Capacity Planning for Micro-solar Power Sensor Networks. In Proceedings of the 2008 International Conference on Information Processing in Sensor Networks (ipsn 2008), 22-24 April 2008, 2008; pp. 407–418. [Google Scholar]
- Somvanshi, S.; Islam, M.M.; Chhetri, G.; Chakraborty, R.; Mimi, M.S.; Shuvo, S.A.; Islam, K.S.; Javed, S.; Rafat, S.A.; Dutta, A. From tiny machine learning to tiny deep learning: A survey. ACM Computing Surveys, 2025. [Google Scholar]
- Raza, U.; Kulkarni, P.; Sooriyabandara, M. Low Power Wide Area Networks: An Overview. IEEE Commun. Surv. Tutor. 2017, 19, 855–873. [Google Scholar] [CrossRef]
- Sedra, A.S.; Smith, K.C.; Carusone, T.C.; Gaudet, V. Microelectronic Circuits; Oxford University Press, 2020. [Google Scholar]
- Franco, S. Design with Operational Amplifiers and Analog Integrated Circuits; McGraw-Hill, 1988. [Google Scholar]
- Horowitz, P.; Hill, W. The Art of Electronics; Cambridge University Press, 2015. [Google Scholar]
- Nilsson, J.W.; Riedel, S.A. Electric Circuits; Prentice Hall, 2011. [Google Scholar]
- Arik, S.O.; Kliegl, M.; Child, R.; Hestness, J.; Gibiansky, A.; Fougner, C.; Prenger, R.; Coates, A. Convolutional recurrent neural networks for small-footprint keyword spotting. arXiv 2017, arXiv:1703.05390. [Google Scholar]
- Kim, B.; Chang, S.; Lee, J.; Sung, D. Broadcasted residual learning for efficient keyword spotting. arXiv 2021, arXiv:2106.04140. [Google Scholar]











| Component | Value |
|---|---|
| R1 R2 C1 C2 C3 |
22 kΩ 10 kΩ 1μF 4.7 μF 1 nF |
| Parameter | Value |
|---|---|
| Sampling Rate: Clip duration: k Mel-Band |
22050 Hz 4 s 128 |
| Configuration | Net cost of inference |
Accuracy | Ω |
|---|---|---|---|
| Single Processor Always-on | 3352 s | ≥ 90% * | - |
| Proposed Architecture without EFD | 134.08 s | 78.49% | 837 |
| Proposed Architecture with EFD set for I | 46.24 s | 90.66% | 289 |
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