A 72-Gb/s/pin PAM-3 Transmitter With Asymmetric Reconfigurable Feedforward Equalizer and Edge-Shaping Crosstalk Cancellation

This work presents a high-speed, energy-efficient 72-Gb/s/pin PAM-3 transmitter (TX) implemented in 28-nm CMOS technology. To overcome inter-symbol interference (ISI) and far-end crosstalk (FEXT) in single-ended memory interfaces, two primary innovations are proposed : 1) An Asymmetric Reconfigurable Feedforward Equalizer (AR-FFE) that employs a selectively activated booster to dynamically enhance major symbol transitions, achieving a 60\% improvement in total eye area compared to conventional FFE; 2) An Edge-Shaping Crosstalk Cancellation (ES-XTC) circuit that utilizes look-ahead logic to adaptively suppress data-dependent FEXT from adjacent channels. Operating at 72 Gb/s with a 1.0 V supply, the TX achieves an energy efficiency of 0.93 pJ/bit. This architecture provides a scalable solution for next-generation AI and high-performance computing interconnects.