Exploiting Static Conductance and Dynamic Switching of Memristors for Artificial Intelligence Applications

1. Introduction

The scale and computational demands of artificial intelligence (AI) models have grown explosively in recent years. In this work, AI is broadly defined to encompass a wide spectrum of computational paradigms, including traditional machine learning, deep neural networks, transformer-based foundation models, as well as neuromorphic and bio-inspired learning approaches. From large pre-trained foundation models to real-time inference on resource-constrained edge devices, modern AI workloads impose increasingly stringent requirements on computing power, memory bandwidth, and energy efficiency. However, conventional digital computing architectures, which rely heavily on sequential execution, struggle to meet these demands efficiently [1]. This challenge is further exacerbated by the slowdown of Moore’s Law, which has limited the performance gains achievable through transistor scaling [2]. Meanwhile, traditional von Neumann architectures suffer from significant energy and latency overheads due to the frequent transfer of large volumes of data between physically separated processing and memory units [3,4,5]. Consequently, developing novel computing architectures that enhance parallelism and minimize data movement has become a critical necessity for next-generation AI systems.

Memristors—two-terminal electronic elements with programmable conductance—have emerged as promising building blocks for in-memory computing (IMC) and brain-inspired hardware [6,7,8]. As illustrated in Figure 1, their functionality is fundamentally characterized by two key properties: (i) static conductance—the ability to set and retain an analog (or multi-level) conductance that can represent matrix elements; and (ii) dynamic switching—nonvolatile or volatile, time-dependent resistive dynamics that enable the implementation of perceptron-like neuron behavior, short-term synaptic plasticity, stochastic transitions, and other temporal primitives.

Exploiting the static conductance of memristors arranged in crossbar arrays, a primary application is analog matrix computing (AMC), which enables massively parallel, low-energy operations. The AMC paradigm encompasses two major pathways. The first is matrix-vector multiplication (MVM), the fundamental operation in fully connected, convolutional, and attention-based layers of neural networks [9]. The second pathway extends AMC to the direct, one-step solution of matrix equations [10]. This is achieved through closed-loop circuits that integrate crossbars with feedback amplifiers to perform matrix inversion, generalized inverse and related linear solving tasks in the analog domain.

Dynamic switching behavior refers to time-dependent resistive changes and switching events in memristors. Such dynamics enable a wide range of temporal and logic functions [11,12,13,14]. Stateful logic and attractor networks typically rely on nonvolatile memristors, as these applications require deterministic switching behavior and long-term retention. In contrast, devices exhibiting controlled decay, thresholding, or stochastic switching can function as compact physical neurons, implement local spike-timing-dependent plasticity (STDP), realize reservoir computing substrates, or serve as on-chip sources of randomness for probabilistic inference. In practice, hybrid designs that combine volatile temporal processors with nonvolatile readout or storage allow systems to integrate short-term dynamics with long-term weight storage.

This Review frames memristor-based AI hardware around these two complementary device capabilities—static conductance and dynamic switching—and systematically surveys physical mechanisms, key electrical metrics, representative system-level implementations, and remaining challenges. After an overview of device physics and performance metrics (Section 2), we examine static-conductance approaches for parallel and analog matrix computations (Section 3) and dynamic-switching approaches for stateful logic, attractor network, reservoir computing, temporal processing, STDP and stochastic computation (Section 4). We conclude with a synthesis of open problems and a perspective on co-design strategies that bridge materials, circuits and algorithms. This review ultimately seeks to guide future efforts in developing robust, scalable, and application-tailored memristor-based AI systems.

2. Memristor Background

The memristor concept was first proposed by Leon Chua (1971) and later experimentally demonstrated in nanoscale two-terminal devices [15,16]. Fundamentally, a memristor encodes the history of applied electrical stimuli into a programmable resistance (or conductance) state. In practice, most hardware implementations adopt a metal–insulator–metal (MIM) “sandwich” structure, where a thin active layer—typically only a few nanometers thick—is positioned between the top and bottom electrodes. The composition of the active material and the engineered electrode interfaces determine the dominant switching mechanism and, consequently, the device’s electrical characteristics.

The switching physics of modern memristors can be broadly categorized into several well-established mechanisms. A major class comprises nonvolatile resistive switching processes, including the valence-change mechanism (VCM), electrochemical metallization (ECM), and phase-change memory (PCM). In VCM-based devices, resistive switching originates from the field-driven migration of oxygen vacancies in oxides such as HfO₂ or TaOx, resulting in the formation and rupture of conductive filaments (CFs) under voltage bias [17,18,19,20]. Similarly, ECM devices operate through the migration and electrodeposition of active metal ions (e.g., Ag⁺ or Cu²⁺), which form or dissolve metallic conductive paths [21,22]. Notably, both VCM and ECM behaviors can be described within a unified voltage-driven ion migration framework, where defect or metal-ion motion governs the resistive states [3]. In PCM devices, resistance modulation arises from reversible phase transitions between amorphous (high-resistance) and crystalline (low-resistance) states in chalcogenide materials such as Ge–Sb–Te, triggered by Joule heating and rapid quenching [23,24]. These nonvolatile devices hold strong potential for high-density memory and in-memory computing applications.

In addition to nonvolatile devices, volatile or threshold-type memristors spontaneously return to a high-resistance state once the external stimulus is removed, making them well-suited for dynamic and temporal computing [25,26,27]. Representative examples include diffusion-mediated memristors, Ovonic threshold switching elements, and VO₂-based Mott devices. Such volatility is particularly valuable for implementing short-term memory and temporal filtering in reservoir computing and compact neuronal models. These categories are not strictly distinct: material selection, interface engineering, current compliance, and pulse protocols can tune a device’s behavior along a continuum from volatile to nonvolatile on the same platform [6]. Therefore, practical classification is often application-driven. From this perspective, it is useful to adopt consistent terminology: in this review, static conductance refers to conductance states intended for long-term weight storage and computation, whereas dynamic switching refers to resistive state transitions exploited for stateful logic, attractor networks, temporal processing, and plasticity.

Key device performance metrics that determine suitability for AI workloads include: settling and retention times, programming linearity and symmetry, multilevel resolution, cycle-to-cycle and device-to-device variability, endurance, on/off contrast, switching energy, and the probability of stochastic switching under a given input pulse. Subsequent sections discuss how these physical characteristics are leveraged in specific circuit implementations and algorithmic frameworks.

3. Static Conductance of Memristors and Their Applications in AI

3.1. Matrix-Vector Multiplication Primitive on Crossbar Arrays

A memristor crossbar array serves as a fundamental building block for IMC, efficiently performing MVM [28,29,30,31,32]. As shown in Figure 2a, the array stores programmable conductances $A_{ij}$​ at each crosspoint, representing the weight matrix A. When a voltage vector $\mathit{x}$ is applied to the word lines (WLs), the current flowing through each device is $I_{ij}=A_{ij}\cdot x_j$​. According to Kirchhoff’s current law (KCL), the total current in each bit line (BL) is the sum of the currents from all connected devices: $I_i={\mathsf{\Sigma }}_j{G}_{ij}{v}_j$. This current represents exactly the dot product between the i-th WL of the conductance matrix and the input vector. The resulting currents are then converted into a digital MVM result by peripheral circuitry, including transimpedance amplifiers (TIAs) and analog-to-digital converters (ADCs).

MVM executes n-dimensional dot products in a single physical step across a crossbar array, providing massive parallelism that can outperform serial digital implementations. IMC leverages this property to perform computation where the weights are stored, avoiding repeated data transfer between memory and processor. However, this crossbar-based implementation of MVM only partially alleviates the von Neumann bottleneck: the array typically stores only the weight matrix, while input values must still be supplied from external sources. To address this limitation, Wang et al. propose a dual in-memory computing method where the input vector is also represented as conductance states within the array, as shown in Figure 2b [33]. In this approach, a voltage pulse is applied to the word line corresponding to the row that stores the input vector $\mathit{x}$. As a result, the bit-line (BL) voltages are modulated according to KCL. By introducing conductance compensation ($g_c$​) to equalize the total conductance connected to each BL, a linear mapping between BL voltage and input value can be achieved: ${\mathit{V}}_{BLj}=k\mathit{x}$, where k is a constant. This approach enables both weights and inputs to be processed within the array, eliminating the need for digital-to-analog converters (DACs) for input encoding, thereby significantly reducing external data movement and improving array utilization.

This parallel MVM primitive, implemented at the physical device level, is a cornerstone for accelerating linear operators in a wide range of neural network architectures. However, in terms of precision, practical implementations have typically achieved effective resolutions of approximately 5–8 bits for specific tasks [34].

3.2. Applications of MVM in Neural Networks

A Memristor crossbars offer a versatile MVM primitive capable of accelerating a wide range of neural network architectures, and extensive research has demonstrated their practical integration.

Fully Connected Network (FCN). A fully connected layer computes $\mathit{y}=\dot{\mathit{W}}\cdot \mathit{x}+\mathit{b}$, as illustrated in Figure 3a. Mapping this operation onto a crossbar is straightforward: each weight $W_{ij}$ is programmed as a conductance $A_{ij}$, and the input vector $\mathit{x}$ is applied as WL voltages; the resulting BL currents represent the output activations [35,36,37,38,39]. Because dense MVMs dominate many AI workloads, crossbars deliver high throughput by performing numerous dot products in parallel. Representative works span device-to-system considerations: integration studies combine arrays with CMOS peripherals to form programmable systems on a chip (SoC) that tolerate variability via calibration [35]; Dot-Product Engine–type architectures explore weight encoding, negative-value mapping, and precision decomposition [40]; and mixed-precision approaches perform most dot products in low-precision analog and correct residuals digitally, achieving efficient energy–accuracy tradeoffs [29]. FCNs represent a well-established and promising target for crossbar-based acceleration, with substantial progress already demonstrated in practice.

Convolutional Neural network (CNN). A convolution operation can be formulated as multiple local dot products between flattened kernels and input patches, as illustrated in Figure 3b [41]. Consequently, convolutions map naturally to memristor crossbars by storing flattened kernels as column-wise conductance vectors and applying input patches as row voltages [34,42,43,44,45]. The primary challenges lie in limited array sizes and efficient input reuse. Key studies have addressed these issues through weight encoding and precision-splitting schemes to reduce column replication, as well as optimized tiling and reuse strategies to improve array utilization. Moreover, several fully hardware-implemented CNN prototypes have demonstrated the feasibility of end-to-end on-chip inference [9,40,46]. Together, these results confirm that, with proper mapping and peripheral co-design, memristor crossbars can effectively accelerate convolutional layers.

Recurrent neural Network (RNN). Recurrent models reuse the same weight matrices across time steps, so the principal operations remain MVMs of the form $\mathit{W}\cdot {\mathit{x}}_{\mathit{t}}$ and $\mathit{W}\cdot {\mathit{h}}_{\mathit{t}-1}$ for the gates and candidate updates in an LSTM cell, as illustrated in Figure 3c [47]. Memristor crossbars can store the weight matrices for input and recurrent connections and be invoked at each time step to perform the required MVMs in parallel [48,49,50,51,52]. In practice, however, the time-recursive nature of RNNs raises two additional requirements: maintaining stable programmed conductances over repeated reads and writes, and controlling accumulated numerical errors across multiple time steps. Experimental and system-level studies have addressed these challenges: early demonstrations verified low-power LSTM inference, followed by in-situ training approaches that adapt to device nonidealities and system prototypes that incorporate calibration and mixed-precision correction [48,50]. Achieving high-precision conductance programming is particularly crucial to prevent long-term error accumulation.

Graph Neural Network (GNN). A prototypical graph convolutional layer (GCN) implements $\mathit{H}(l+1)=\sigma (\widehat{\mathit{A}}\cdot \mathit{H}\left(l\right)\cdot \mathit{W}(l\left)\right)$,where $\widehat{\mathit{A}}$ is an adjacency matrix and $\mathit{H}\left(\mathit{l}\right)$ is the node-feature matrix of the l-th layer, as illustrated in Figure 3d [53]. Because adjacency matrices are sparse and access patterns irregular, directly mapping GNN operations onto dense crossbars results in low utilization and significant energy inefficiency [54,55]. Recent studies have proposed sparse-friendly mappings, communication support, and heterogeneous architectures that decouple the aggregation and dense transformation stages. For example, IMA-GNN organizes dataflow around graph aggregation, while ReGNN partitions dense and sparse computations for improved efficiency [56,57]. These works demonstrate that, with sparsity-aware scheduling and heterogeneous compute support, crossbar-based GNN accelerators can achieve competitive performance [58,59,60].

Transformer. The computational bottleneck of Transformers lies in repeated dense matrix multiplications, prominently including the generation of Query ($\mathit{Q}$), Key ($\mathit{K}$), and Value ($\mathit{V}$) matrices through matrix multiplications of input embeddings. Subsequently, the scaled dot-product attention computes attention scores through another matrix multiplication ($\mathit{Q}{\mathit{K}}^{\mathrm{T}}$), followed by a weighted sum with $\mathit{V}$, expressed as $\mathrm{S}\mathrm{o}\mathrm{f}\mathrm{t}\mathrm{m}\mathrm{a}\mathrm{x}\left(\mathit{}\mathit{Q}\cdot {\displaystyle \frac{{\mathit{K}}^T}{\sqrt{d_k}}}\right)\cdot \mathit{V}$, as illustrated in Figure 3e [61]. Unlike many CNN kernels, the operands in attention layers vary dynamically at runtime, and generative inference requires storing and reusing key/value projections from previously generated tokens. Major challenges include minimizing frequent writes of intermediate results and reducing ADC/DAC overhead. Recent solutions address these issues through architectural and algorithmic co-design: ReTransformer employs matrix decomposition and pipelined execution; X-Former introduces sequence blocking for long-context processing; and analog in-memory attention approaches retain token projections in analog or hybrid storage to reduce data movement and latency during generation [62,63,64]. These works indicate that with co-optimized dataflow and approximation strategies, memristor crossbars can efficiently accelerate attention mechanisms in Transformer models [65,66,67,68].

Spiking Neural Network (SNN). Spiking networks compute weighted sums of sparse, temporally coded spike trains, meaning their synaptic operations can be expressed as dot products between spike-based inputs and conductance-encoded weights, as illustrated in Figure 3f. In addition, some volatile or diffusive memristors inherently exhibit thresholding and short-term dynamic behaviors, enabling compact hardware neuron implementations that integrate seamlessly with synaptic crossbars [69]. Architectures combining sensing, event encoding, spike generation, and crossbar-based synapses minimize I/O overhead and enable highly event-driven computation pipelines. Several studies have also explored on-chip learning rules, such as STDP and its variants, implemented through local updates [70]. Overall, memristor hardware has demonstrated the ability to support both the synaptic MVMs and the compact neuronal primitives necessary for building dense, low-power SNN accelerators.

3.3. Analog Matrix Equation Solving Circuits

Memristor crossbars can also be employed to implement efficient analog matrix equation solvers [10,71]. By constructing closed-loop feedback topologies in which crossbars are embedded within the feedback paths of amplifiers—such as operational amplifiers (op-amps) or transimpedance amplifiers (TIAs)—these analog matrix computing (AMC) circuits can perform more advanced linear algebra operations relevant to AI applications. Figure 4 summarizes several representative closed-loop AMC circuits, including those for matrix inversion, pseudoinversion, eigenvector extraction, and sparse approximation.

Matrix Inversion (Figure 4a). The inversion circuit (INV) solves the linear system $\mathit{A}\cdot \mathit{x} =\mathit{y}$ for an n×n matrix $\mathit{A}$. The crossbar that encodes $\mathit{A}$ is connected in a global feedback loop through op-amps. Thanks to the op-amp virtual-ground property, the input nodes are maintained at approximately 0 V during operation. When an input current vector -y is applied to the op-amp inputs, invoking KCL at the op-amp input gives

$$I_i =-y_i+\sum _j{A}_{ij} x_j=-y_i+{\left(\mathit{A}\cdot \mathit{x}\right)}_i$$

Because the op-amp input draws negligible current in steady state, the closed loop enforces $-\mathit{y}+\mathit{A}\mathit{x} = 0$, leading to the steady-state output

$$\mathit{x}={\mathit{A}}^{-1}\cdot \mathit{y}$$

Including op-amp dynamics using a single-pole model shows that the output evolves continuously from an initial condition toward this steady-state solution [72]. The transient behavior satisfies a first-order differential equation of the form

$${\displaystyle \frac{d\mathit{x}}{dt}}={\displaystyle \frac{1}{\tau }} \mathit{U} (\mathit{A}\cdot \mathit{x}-\mathit{y})$$

where $\tau$ is the circuit time constant and $\mathit{U}$ is a diagonal scaling matrix. The convergence time of this topology depends on the spectral properties of $\mathit{A}$ (in particular its smallest eigenvalue), rather than directly on matrix size [72]. Specifically, a larger minimum eigenvalue (or equivalently, a smaller condition number) leads to faster convergence. This spectral dependence explains why closed-loop AMC can achieve very fast solutions for well-conditioned matrices.

Generalized Inverse (Figure 4b–c). Non-square or rank-deficient problems require a generalized inverse (GINV). AMC can realize both left and right GINVs with paired crossbars and amplifier networks.

Figure 4b shows the left GINV circuit for the overdetermined case m > n. Two crossbar arrays store copies of $\mathit{A}$ and two sets of amplifiers form the feedback network. When the input current vector y is applied, the first crossbar and its TIAs produce WL voltages z proportional to the residual ($\mathit{y}-\mathit{A}\mathit{x}$):

$$\mathit{z}=-\alpha (\mathit{y}-\mathit{A}\cdot \mathit{x})$$

Applying KCL on the second crossbar column lines yields

$${\mathit{A}}^T\cdot (\mathit{y}-\mathit{A}\cdot \mathit{x})=0$$

So the steady-state solution is

$$\mathit{x}={\left({\mathit{A}}^T\cdot \mathit{A}\right)}^{-1}\cdot {\mathit{A}}^T\cdot \mathit{y} = {\mathit{A}}^{+}\cdot \mathit{y}$$

Figure 4c implements the right GINV for the underdetermined case m < n. Here the crossbars are programmed with ${\mathit{A}}^T$ and the topology is modified so that KCL yields

$$-\mathit{y}-\alpha \mathit{A}\cdot {\mathit{A}}^T\cdot \mathit{z} = 0 => \alpha \mathit{z} = -{\left(\mathit{A}\cdot {\mathit{A}}^T\right)}^{-1}\cdot \mathit{y}$$

and back-substitution gives

$$\mathit{x}=-\alpha {\mathit{A}}^{\mathit{T}}\cdot \mathit{z}={\mathit{A}}^{\mathit{T}}\cdot {\left(\mathit{A}\cdot {\mathit{A}}^{\mathit{T}}\right)}^{-1}\cdot \mathit{y}={\mathit{A}}^{+}\cdot \mathit{y}$$

Both circuits compute minimum-norm solutions through fully analog feedback dynamics, which is useful for least-squares regression tasks in AI.

Eigenvector Circuit (Figure 4d). If a TIA conductance encodes the derivative associated with an eigenvalue , the closed-loop dynamics enforce the eigenvalue equation

$$\mathit{A}\cdot \mathit{x} =\lambda \mathit{x}$$

By KCL, currents leaving each row correspond to $\mathit{A}\cdot \mathit{x}$; after conversion and scaling the circuit implements $\mathit{A}\cdot \mathit{x} =\lambda \mathit{x}$ [73]. The steady-state outputs are the eigenvector associated with $\lambda$. This analog approach enables direct extraction of principal directions, which can accelerate PCA and spectral methods used in AI pipelines [74].

Modified-GINV Circuit (Figure 4e). Fig. 4e illustrates an AMC circuit designed to solve for all eigenpairs (eigenvalues and eigenvectors) of a matrix [75]. This design, derived from the GINV circuit topology, operates by disconnecting one column feedback path and mapping the target matrix $\mathit{A}$ and the diagonal matrix $\lambda \mathit{I}$ onto two distinct memristor arrays. Leveraging KCL, Ohm’s law, and the virtual short and virtual ground principles of op-amps, the circuit inherently satisfies the following matrix relation:

$${\left(\mathit{A}-\lambda \mathit{I}\right)}_{2:n}^T {\left(\mathit{A}-\lambda \mathit{I}\right)}_{2:n} {\mathit{x}}_{2:n} = -{\left(\mathit{A}-\lambda \mathit{I}\right)}_{2:n}^T {\left(\mathit{A}-\lambda \mathit{I}\right)}_1 x_1$$

In this formulation, the vector ${\left(x_1,x_2 ,\dots ,x_n\right)}^T$ corresponds to the eigenvector associated with the current eigenvalue parameter $\lambda$. By sweeping the conductance values of the diagonal array to vary $\lambda$ and monitoring the output voltage of the op-amp in the disconnected branch for a characteristic peak, the circuit can identify when $\lambda$ coincides with an actual eigenvalue of $\mathit{A}$. This approach enables the extraction of the complete set of eigenpairs for a given matrix, which can accelerate various AI applications that rely on eigendecomposition, including principal component analysis (PCA), spectral clustering and graph learning.

Sparse Approximation (Figure 4f). Figure 4f shows an AMC circuit that solves a sparse approximation (LASSO-like) problem:

$$\underset{x}{\mathit{min}}L\left(\mathit{x}\right) =\underset{x}{\mathit{min}}[1/2 || \mathit{y}-\mathit{A}\cdot \mathit{x} {\left.|\right|}_2^2 +\lambda || \mathit{x} {\left.|\right|}_1]$$

where $\lambda$ controls the sparsity penalty [76]. In this design, the compensation conductance g_c is applied to let the conductance sum of each column equal to a constant, thus each column-line voltage is set by the mismatch $-\mathit{y}+\mathit{A}\cdot \mathit{x}$, yielding a crossbar output current proportional to ${\mathit{A}}^{\mathit{T}}(\mathit{A}\mathit{x}-\mathit{y})$. That current is converted by TIAs to node voltages μ, and the sparsity outputs x is obtained through soft-thresholding nonlinearity (implemented by an analog threshold module, as shown in Figure 4g). Element-wise thresholding produces the solution vector x via a simple nonlinear map:

$$\mathit{x} = \mathrm{m}\mathrm{a}\mathrm{x}[ \mathit{\mu } -\lambda , 0 ]$$

which acts as a hardware proximal operator for the L1 term under a nonnegativity assumption. The analog inverters are applied for cancelling the diagonal contribution of the Gram product ${\mathit{A}}^{\mathit{T}}\cdot \mathit{A}$. The circuit performs the locally competitive algorithm (LCA):

$${\displaystyle \frac{d\mathit{\mu }}{dt}} = {\displaystyle \frac{1}{\tau }} [-\mathit{\mu }+{\mathit{A}}^{\mathit{T}}\cdot \mathit{y}-({\mathit{A}}^{\mathit{T}}\cdot \mathit{A}-I)\cdot \mathit{x}]$$

This direct analog implementation of the differential equation can accelerate sparse coding, compressed sensing, and other AI primitives relying on L1 regularization.

These closed-loop AMC circuits convert physical parallelism and feedback dynamics into direct, analog solvers for linear-algebra problems central to AI. Thereby, they provide efficient hardware primitives for tasks such as regression, optimization, and neural network training.

3.4. Applications of Analog Matrix Equation Solving Circuits

3.4.1. Linear/Logistic Regression

As a fundamental machine learning (ML) model, linear regression is widely used for regression and predictive analysis across diverse fields, including biology, statistics and finance [77]. The GINV circuit described above can be directly applied to perform linear regression in a single step and has been demonstrated on standard benchmark datasets such as the Boston Housing dataset [78]. This approach enables one-step regression with comparable accuracy to digital baselines and offers a dramatic speedup and energy reduction owing to its fully parallel analog implementation [78]. In contrast to linear regression, which is a fully linear model, logistic regression introduces a nonlinear sigmoid function into the feature-to-output mapping to produce binary outcomes. As a widely used model for object classification and pattern recognition, logistic regression can be regarded as a single-layer feedforward neural network. It is also commonly employed as the final output layer in multilayer neural networks, with its training process equivalent to that of a single-layer network. Through the logit transformation, the logistic regression problem can be reduced to a linear regression problem. Based on this simplification, as shown in Figure 5a, the aforementioned linear regression (or GINV) circuit has been shown to implement logistic regression in one step—for example, in the training of a two-layer neural network for MNIST digit recognition and can effectively accelerate reservoir computing training [78,79,80]. Previous studies have also demonstrated that such circuits exhibit significant performance advantages across multiple benchmark metrics [81,82,83,84,85]. Their computational speed can further be enhanced through parameter co-optimization [86].

Building on the basic GINV circuit structure, a generalized regression circuit has also been designed by replacing scalar conductances with a conductance array. The introduced matrix enables encoding additional information on data covariance for generalized linear regression or circuit preconditioning when solving linear systems [87]. Meanwhile, a ridge regression circuit has been developed to implement the regularization term by adding an additional negative feedback branch [88]. Although applications of generalized and ridge regression circuits in neural network training have not yet been reported, these designs have significantly broadened the functional scope of regression circuits and are expected to enable fully on-hardware neural network training [89].

3.4.2. Second-Order Neural Network Training

In deep neural network (DNN) training, second-order optimization methods converge much faster than first-order ones because they leverage the inversion of the second-order information (SOI) matrix to determine more accurate descent directions and step sizes [90]. However, on conventional computing platforms such as GPUs and CPUs, handling the massive SOI matrix incurs substantial computational and memory overhead. As illustrated in Figure 5b, the matrix inversion circuit described earlier can efficiently accelerate SOI matrix inversion, offering O(1) computational complexity and high parallelism. Analysis has shown that, compared with GPUs and PipeLayer (a framework for large-scale DNNs), the second-order training accelerator based on RRAM matrix inversion circuits achieves an average speed-up of 115.8×/11.4× and an average energy efficiency improvement of 41.9×/12.8× [91]. In parallel, inspired by the intrinsic mechanisms of analog matrix computing, the thermodynamic approach to computation has emerged as a promising paradigm for solving mathematical problems. Its core principle lies in exploiting the stochastic dynamic behavior of physical systems governed by the interplay of conservative, dissipative, and fluctuating forces [92]. Thermodynamic computing has been shown to accelerate tasks such as matrix determinant evaluation, and matrix equations solving [93,94]. Furthermore, it has been applied to Bayesian inference and to accelerating various second-order neural network training algorithms, including natural gradient descent and Kronecker-factored approximate curvature (KFAC) [95,96,97]. Notably, these thermodynamic approaches have demonstrated superior speed and energy efficiency compared with first-order methods such as stochastic gradient descent (SGD) and Adam.

3.4.3. Linear Programming

The parallelism of AMC circuits, combined with feedback-loop architectures, enables their widespread application in optimization tasks, including linear programming (LP) and quadratic programming (QP). LP and QP are extensively used in numerous scientific and engineering fields, such as machine learning, robot kinematics, drone control, resource allocation, and digital finance [98]. Currently, industry relies primarily on digital solvers, including optimized versions of the simplex and interior-point methods, to solve LP and QP problems. However, as matrix sizes grow, digital computers face increasing difficulty in solving these problems efficiently, while real-time applications demand faster solution speeds. LP and QP problems can be formulated as minimizing an objective function ${\mathit{x}}^T\mathit{Q}\mathit{x}+{\mathit{c}}^T\mathit{x}$ subject to equality and inequality constraints, where a QP problem reduces to an LP problem when the $\mathit{Q}$ matrix is zero. Both the interior-point and simplex methods are iterative, with each iteration requiring multiple complex matrix computations, which imposes a lower bound on computational complexity for digital solvers [99,100]. AMC circuits provide an alternative approach by directly accelerating these matrix operations. For example, using AMC circuits to implement iterative methods such as the Alternating Direction Method of Multipliers can reduce the effective computational complexity of QP problems to approximately O(k), where k is the iteration times that is typically small. Furthermore, optimized circuit structures can extend AMC solvers to tackle more complex problems, including mixed-integer programming [101,102].

By fully exploiting the inherent differential characteristics of feedback loops, several studies have proposed LP solvers based on recurrent neural network architectures and direct analog solvers [103,104,105,106,107]. As shown in Figure 5c and Figure 5d, the ultra-fast hybrid computing system integrates tuning, control, optimization, reading circuits, and memristor arrays. By directly mapping the problem constraints and objective function to the memristor array conductances and input voltage values, the solution can be obtained in a single step at the output port, reducing the computational complexity of LP and QP optimization to O(1). Experimental testing has shown that this system can solve optimization problems within 1 μs. In application scenarios such as miniature aerial vehicle control and edge computing for clinical image analysis, the memristor-based analog LP and QP problem solver demonstrates ultra-fast response speeds and energy efficiency improvements of over seven orders of magnitude, substantially alleviating computational pressure in these domains.

3.4.4. PCA and Spectral Clustering

PCA is a classical linear dimensionality reduction technique in machine learning. It relies on the eigendecomposition of data covariance matrices to extract eigenvectors (principal components) representing directions of maximum variance, with corresponding eigenvalues quantifying the information content. Conventional digital processors implement PCA using singular value decomposition or iterative algorithms, incurring $O(n³)$ computational complexity for high-dimensional data and suffering from significant data movement overhead. The memristor-based AMC circuit in Figure 4e provides a hardware acceleration solution: by mapping the covariance matrix $\mathit{C}$ onto array conductances and sweeping the $\lambda$ value in the diagonal array, the circuit solves all eigenpairs directly in the analog domain [75,108]. When $\lambda$ coincides with an eigenvalue, the op-amp output exhibits a characteristic peak, while the voltage vector ${\left(x_1, x_2, \dots , xₙ\right)}^T$ directly encodes the corresponding eigenvector. This analog-domain direct solution eliminates the need for iterative convergence and data movement, enabling PCA with ultra-low latency and energy consumption. The circuits have been validated on the Iris dataset and Wine dataset, with extracted principal components closely matching theoretical values.

Spectral clustering is a graph-based clustering algorithm that relies on eigendecomposition of the graph Laplacian matrix $\mathit{L}=\mathit{D}-\mathit{A}$ [109]. Its core step extracts eigenvectors corresponding to the smallest nonzero eigenvalues as node spectral embeddings, followed by k-means clustering in the embedding space to partition graph nodes. For large-scale graphs with tens of thousands of nodes (e.g., social networks, knowledge graphs), Laplacian eigendecomposition imposes enormous computational demands that conventional digital processors struggle to meet for real-time applications. The AMC circuit in Figure 4e provides efficient hardware acceleration: by mapping the Laplacian matrix onto memristor arrays, the circuit completes eigendecomposition in constant time, directly outputting all required eigenvectors. Because the circuit solves the complete set of eigenpairs rather than only the dominant ones, it is particularly suited for spectral clustering, which requires multiple non-dominant eigenvectors corresponding to the smallest eigenvalues. The parallelism and low-latency characteristics of analog computing, combined with memristor in-memory processing, significantly alleviate the memory wall bottleneck in large-scale graph analytics, offering viable acceleration for real-time graph clustering, community detection in social networks, and image segmentation applications [110,111,112].

4. Dynamic Switching of Memristors and Their Applications in AI

Driven by an applied voltage, memristors change their conductance, exhibiting distinct conductance states. The high-conductance state (HCS) functions like a closed switch (logic 1), while the low-conductance state (LCS) acts as an open switch (logic 0). Beyond these static conductance characteristics, the dynamic switching process also enables various AI-related functions, allowing the devices to serve simultaneously as nonvolatile memory elements and in situ logic units.

4.1. Stateful Logic and In-Memory Logic Acceleration

Stateful logic executes Boolean operations directly within a memory array, by exploiting the abrupt switching process of memristor to indicate logic output [113,114,115,116,117,118]. It uses only the two conductance levels HCS and LCS to encode logic 1 and 0, respectively. Under proper voltage stimuli, SET and RESET transitions change a device to HCS or LCS, respectively. In this way, a memristor both stores a bit and participates in logic operation, eliminating costly data movement between separate memory and compute units.

Stateful logic gates operate by exploiting differences in conductance among input memristors to control intermediate node voltages. Those intermediate voltages, in turn, determine whether an output memristor receives a voltage that exceeds its switching threshold and therefore switches state. Different input patterns produce different node voltages and thus different outputs for the same physical connection pattern.

Material implication (IMP) was the earliest demonstrated stateful primitive for memristors [113]. As shown in Figure 6a, in the IMP circuit two memristors, A and Y, together with a load resistor are driven by two voltages: a conditioning voltage $V_{\mathrm{c}\mathrm{o}\mathrm{n}}$ applied to A and a SET voltage $V_{\mathrm{s}\mathrm{e}\mathrm{t}}$ applied to Y. The intermediate node voltage $V_{\mathrm{P}}$ is determined by KCL:

$$V_{\mathrm{P}}={\displaystyle \frac{V_{\mathrm{c}\mathrm{o}\mathrm{n}}{G}_{\mathrm{A}}+V_{\mathrm{s}\mathrm{e}\mathrm{t}}{G}_{\mathrm{Y}}}{G_{\mathrm{X}}+G_{\mathrm{Y}}+G_{\mathrm{L}}}}$$

Here $G_{\mathrm{A}}$ and $G_{\mathrm{Y}}$ are the conductances of A and Y, and G_L denotes the load conductance. The logic design ensures that Y is SET (written to 1) only when A = 0 and Y = 0 initially; when A=1 and Y=0, the node voltage remains below the SET threshold, preventing switching. If Y is already 1, the output stays unchanged. The final state of Y implements the IMP result. IMP, together with FALSE logic gate, can be composed to realize universal logic.

Memristor-Aided LoGIC (MAGIC) is a memristor-only logic family that mainly uses RESET transitions to implement gates such as NOR [114]. As shown in Figure 6b, input memristors A and B are preprogrammed to input values, and the output memristor Y is initially set to HCS. During evaluation, input lines are driven with voltages such that the intermediate node voltage $V_{\mathrm{P}}$ becomes

$$V_{\mathrm{P}}={\displaystyle \frac{V_{\mathrm{A}}{G}_{\mathrm{A}}+V_{\mathrm{A}}{G}_{\mathrm{B}}}{G_{\mathrm{A}}+G_{\mathrm{B}}+G_{\mathrm{Y}}}}$$

If either input is logic 1, $V_{\mathrm{P}}$ shifts and the voltage across Y exceeds its RESET threshold, forcing Y to LCS (logic 0). Only if both inputs are 0, Y remains in HCS (logic 1). With NOR as a primitive, arbitrary Boolean logic can be synthesized in place within the array.

Stateful logic can be extended to the so-called stateful neural network framework [115]. As shown in Figure 6c, memristors A and B encode the logic inputs, and the output memristor Y stores the computation result. Applying KCL at an intermediate node, the voltage across the output memristor can be expressed as a weighted sum of input contributions:

$$V_{\mathrm{Y}}-V_{\mathrm{P}} = w_{\mathrm{A}}{x}_{\mathrm{A}}+w_{\mathrm{B}}{x}_{\mathrm{B}}+b$$

Here $x_{\mathrm{A}}$ and $x_{\mathrm{B}}$ denote input bits stored in memristor states, and $w_{\mathrm{A}}$, $w_{\mathrm{B}}$, $b$ are effective weight terms derived from conductances and voltage biases. Because the output memristor has a switching threshold, the architecture naturally implements a nonlinear activation: if the weighted sum exceeds threshold, the output switches to 1; otherwise it remains 0. In this way, linear accumulation and a threshold activation are realized in situ, enabling implementation of single-layer perceptron for linearly separable logic functions, and, by cascading, multi-layer networks capable of XOR/XNOR and other linearly inseparable functions.

Using combinations of stateful gates, one can build digital adders, multipliers, and full arithmetic units inside memristive arrays. For example, a 1-bit full adder can be mapped to a column of memristors and a sequence of stateful operations, as shown in Figure 6d and Figure 6e. Researchers have proposed MAGIC-based designs for fixed-point multiplication and for floating-point multiplication adapted to crossbar arrays [119]. Such adders and multipliers can be composed to implement MVM primitives, which are central to neural network inference and training. Complex nonlinear functions and gradients required by learning algorithms can be approximated by Taylor expansions and implemented using the same basic arithmetic primitives.

Several stateful processing-in-memory (PIM) architectures are built upon these MAGIC-based stateful logic primitives to accelerate AI workloads. As shown in Figure 6f and Figure 6g, FloatPIM is a representative architecture that decomposes high-precision operations into sequences of bitwise stateful gates and maps them efficiently onto crossbar arrays [120]. FloatPIM and related systems implement convolution and fully connected layers by bit-serial or hybrid mappings, trading the number of bitwise cycles for reduced data movement and high array parallelism [119,120,121,122,123]. Other architectures—ConvPIM, RIME, ReHy_A, and DUAL—apply similar principles for CNNs, transformers, clustering, and other ML tasks [126,127]. Improvements in mapping, gate synthesis, and compiler-level scheduling are critical to achieve high throughput. On the other hand, hybrid analog–logic approaches may also be applied by combining analog crossbar MVM for bulk multiply–accumulate with stateful digital logic for activations, normalization, and control, thus maximizing the strengths of both paradigms [128].

4.2. Attractor Network

Beyond utilizing the inherent unidirectional threshold behavior of memristor, their SET/RESET switching characteristics can also be leveraged simultaneously. This manifests as a significant hysteresis loop in the conductance-voltage (G-V) plot. Building on this observation, Li et al. first proposed that memristor intrinsically function as an artificial neuron, providing a hysteretic nonlinear activation function [129]. Furthermore, they proved that a circuit comprising a column of memristor connected to a grounded resistor (Figure 7a) constitutes an attractor network, with the externally applied voltage defining an antisymmetric weight matrix (Figure 7b). This network operates via KCL, enabling recursive behavior through device interactions. Specifically, each device’s state change couples dynamically to all others, and a resistance shift in one device generates circuit feedback that propagates changes throughout the network.

Attractor networks are primarily employed for associative memory, wherein attractors store memory content. As the network stabilizes, other states converge towards these corresponding attractors, achieving the associative memory recall. By formulating an energy function for memristor network and analyzing its properties, this work demonstrated that state transitions require overcoming an energy threshold (Figure 7c). This enables the network to store more attractors (a fraction of 2^N), surpassing the linear capacity scaling in current Hopfield networks [11,130,131,132]. Furthermore, previous implementations typically require specialized circuit designs and utilize relatively expensive amplifier circuits as neurons, suffering significant latency and power consumption penalties. In contrast, memristor network comprises simple memristor arrays, where feedback operates continuously under KCL and accelerates attractor dynamics convergence.

4.3. Reservoir Computing and Spatiotemporal Signal Detection with Dynamic Memristors

Volatile memristors are particularly well suited for temporal and spatiotemporal processing. Their internal ionic or defect dynamics provide a controllable fading memory and intrinsic nonlinearity. The fading memory originates from migration and relaxation processes, which cause device responses to decay over characteristic time scales [79,133,134]. As a result, recent inputs strongly influence the current state, while the impact of older inputs gradually diminishes. This combination of short-term memory and nonlinear transduction makes dynamic memristors natural candidates for hardware reservoir computing [135]. They are also effective for local spatiotemporal feature extraction in edge sensors.

A memristor-based reservoir maps time-varying inputs into a high-dimensional dynamical state. Only the readout layer is trained, keeping training simple and efficient. In hardware, the reservoir is formed by a set of volatile memristors. Their transient conductance changes encode the recent history of input pulses. Nonlinearity in device I–V characteristics and threshold-like switching broaden the feature space. This improves separability of temporal patterns. Practical reservoir designs exploit these device-level properties together with input encoding and simple readout structures. They can perform classification, forecasting, and event detection in real time.

Experimental validation has employed arrays of 88 dynamic memristors to build a compact reservoir. They encoded input sequences as pulse trains and used the devices’ transient responses as reservoir states. A linear readout was trained to classify framed MNIST patterns and to predict nonlinear time series, with the same ionic device dynamics simultaneously providing a fading memory of recent inputs and a nonlinear projection of temporal features. These are essential for framed-digit classification and time-series prediction in a small hardware footprint (Figure 8a and Figure 8b) [136]. To further enhance state richness and resource efficiency, subsequent work combined simple masking with parallel device sampling [137]. This masked-parallel scheme generates virtual nodes from a limited number of physical devices. This approach achieved strong results on spoken-digit recognition and chaotic-series prediction (Figures 7c-7h). They later demonstrated fully analog reservoir stacks with non-volatile memristor readouts. These systems enabled low-power, real-time spatiotemporal processing such as ECG and gesture recognition [138].

Beyond pure RC, dynamic memristors have been integrated into adaptive neuromorphic perception pipelines [139,140,141,142,143,144,145,146,147]. These systems perform local spatiotemporal feature extraction and fast online adaptation. In these systems, memristor arrays implement tunable temporal kernels and rapid state updates that directly influence sensor-level decisions. For example, a differential neuromorphic pipeline was developed that uses memristor dynamics for near-sensor perception [140]. Their system enables fast adaptation in unstructured tasks and robust tactile and scene-level decision extraction in robotic scenarios (Figure 9), achieving low-latency responses by exploiting near-sensor processing that reduces data movement.

4.4. Spike-Timing-Dependent Plasticity

STDP is a local, timing-based synaptic learning rule [148,149]. It adjusts synaptic efficacy according to the relative timing of pre- and post-synaptic spikes. In the commonly used pair rule, the weight change follows

$$\begin{gathered} \mathsf{\Delta }w = A_{+} exp(-\mathsf{\Delta }t/{\tau }_{+}) \mathrm{f}\mathrm{o}\mathrm{r} \mathsf{\Delta }t > 0 \\ \mathsf{\Delta }w = -A_{- } exp(\mathsf{\Delta }t/{\tau }_{-}) \mathrm{f}\mathrm{o}\mathrm{r} \mathsf{\Delta }t < 0, \end{gathered}$$

where $\mathsf{\Delta }t=t_{pre}-t_{post}$. Positive $\mathsf{\Delta }t$ yields potentiation (LTP), and negative Δ$t$ yields depression (LTD) [148].

Hardware demonstrations show that memristors can implement STDP using simple spike protocols [150,151,152,153,154,155,156,157,158,159]. The first hardware evidence of memristive STDP was reported using a nanoscale memristor acting as a synapse in a hybrid system combining CMOS integrate-and-fire neurons with memristive synapses. In this system, the neuron circuit converted relative spike timing into pulse-width information to induce STDP [151]. Building on this foundation, passive memristor crossbars were integrated with analogue leaky-integrate-and-fire (LIF) silicon neurons to experimentally measure the canonical pair-STDP window (Figure 10a) [160]. This work establishes a practical route for device-level STDP in dense arrays. Pair-based STDP cannot capture all biological phenomena. Triplet-STDP models extend the rule by including higher-order spike interactions or trace variables. Devices with additional internal dynamics—so-called second-order memristors—can reproduce triplet effects. Device-level triplet-STDP was demonstrated with weight updates under three-spike protocols (Figure 10b) [161]. The observed behavior matches triplet model predictions and highlights the role of internal device traces in shaping plasticity.

At system scale, STDP has been used for online learning and pattern tracking. Memristive synapses were integrated with simple spiking neurons [162]. Continuous online experiments were conducted in which synaptic weights evolved via STDP while the network learned and tracked spatiotemporal patterns (Figure 10c and Figure 10d). These demonstrations validate that device-level plasticity can be harnessed for autonomous adaptation and unsupervised feature learning in hardware.

Beyond these core demonstrations, several research lines broaden the STDP rule. Studies of memristive stochasticity argue that device randomness can be used as a computational resource rather than only a defect; stochastic updates can improve exploration and generalization in some learning tasks [150]. System and architecture studies emphasize multi-memristor synapses, selector/1T integration, and pulse-engineering as practical routes to scalability and reliability [154,157].

4.5. Memristor-Enabled Stochastic Computation

Memristors exhibit intrinsic, pulse-dependent stochasticity originating from ion migration, filament nucleation/rupture and phase-transition kinetics [163]. Two measurable statistics summarize this behavior. One is the discrete switching probability $p_{\mathrm{s}\mathrm{w}\mathrm{i}\mathrm{t}\mathrm{c}\mathrm{h}}(V,t)$, which captures the chance that a device will transition between states under a given pulse [164,165,166,167,168]. The other is the post-pulse analog conductance distribution, describing the continuous range of conductance values that a device may assume after modulation [169,170,171,172,173,174,175].

This device-level randomness can be repurposed as a computational resource by two complementary approaches. The first primitive is probabilistic bits (p-bits). Under near-threshold excitation a memristor produces a binary outcome whose expectation depends sigmoidally on the applied bias; by controlling the bias one therefore controls the sampling probability. Networks of p-bits realize hardware-native stochastic logic and can implement probabilistic primitives with minimal digital overhead. The second primitive is continuous conductance noise for Bayesian sampling and training. A single write pulse may produce a random conductance change; the distribution of such changes can sometimes be approximated as continuous and, under aggregation of multiple independent device currents, may approach a Gaussian perturbation by the central-limit effect. Such perturbations serve as the physical Langevin noise in memristor-based stochastic gradient Langevin dynamics (mSGLD) and other in-memory Bayesian update schemes.

Two representative experimental studies illustrate these modes. Cu_0.1​Te_0.9/HfO₂Pt diffusive memristors were demonstrated as reliable p-bit sources, with threshold-switching statistics reported and pulse amplitude mapped to sampling probability; small p-bit networks are used to realize stochastic logic (Figure 11a and Figure 11b) [164]. An in-memory deep Bayesian active-learning system was implemented [170]. This system characterizes post-pulse conductance histograms, uses device noise as the Langevin perturbation in mSGLD, and reports improvements in labeling efficiency and system energy for active learning tasks (Figure 11c–e).

Additional works extend and validate these concepts across device types and applications. Versatile stochastic dot-product circuits were demonstrated that exploit controlled device and circuit variability to implement approximate probabilistic MVM operations suitable for edge inference [169]. Threshold-switching memristors have been used to build stochastic neurons, enabling probabilistic spiking and Boltzmann-style sampling in neuromorphic circuits. NbO_x​ metal-insulator transition devices have been reported as self-oscillatory p-bits, broadening the set of physical primitives for probabilistic computing [166].

5. Discussion

Memristor-based accelerators for AI—whether leveraging static analog conductances for dense linear algebra or dynamic resistive switching for temporal processing—share a common hardware foundation and a common set of constraints. In both cases, conductance-programming fidelity and array-level nonidealities fundamentally limit achievable accuracy and scalability.

Key device parameters determine suitability for specific computational primitives. For clarity, two operational modes are distinguished (Table 1). Nonvolatile memristors (e.g., VCM, ECM, PCM-like variants) provide persistent analog conductances and are the preferred substrate for dense MVM and many stateful/deterministic functions (MVM, AMC solvers, stateful logic, attractor networks). Volatile memristors (WOx, Ag/Cu diffusive, threshold-switch variants) exhibit fast decay and spontaneous reset, making them well suited for reservoir computing, many spike-timing-dependent plasticity (STDP) implementations, and probabilistic-bit (p-bit) sampling. Stochastic computing generally follows two routes: (a) continuous noisy weights realized with programmed nonvolatile memristors, or (b) p-bit streams generated by volatile threshold or diffusive devices. Mapping any AI primitive onto hardware therefore begins with selecting device physics that match its functional role—persistence versus fading memory, and deterministic versus stochastic behavior.

Important device metrics include: conductance uniformity (device-to-device consistency), intrinsic stochasticity (cycle-to-cycle variability), conductance range, number of distinct conductance states, programming precision (effective bits), switching voltage and consistency, switching speed or relaxation time, endurance (cycle lifetime), and retention. For example, crossbar-based MVM implementations typically achieves effective precisions of only a few bits—around 5–8 bits in practice for task-specific deployments—necessitating programming and mapping methods that meet precision targets [34].

At the array level, parasitic line resistance, sneak paths, and capacitive coupling distort the intended Ohm/Kirchhoff mappings. IR drops limit array size and skew the effective conductances seen at the periphery [176]. Passive 0T1R arrays are especially susceptible; selector integration, array partitioning, and hierarchical tiling are common mitigation strategies [3]. Peripheral circuits are equally critical: high-throughput MVM requires DACs for row-voltage generation and ADCs (or low-overhead analog integrators/transimpedance amplifiers) for column readout [177]. AMC solvers add further analog constraints, embedding arrays in amplifier feedback loops where bandwidth, offset, and stability become primary design concerns [78]. In dynamic applications, pulse drivers, precise timing generators and neuron interfaces are essential.

Device switching speed and relaxation time constants determine both computational throughput and feasible temporal roles. For reservoir computing or STDP, volatile-device time constants (τ) must align with task memory horizons or spike timing windows [133]. Nonvolatile devices used in online training, stateful logic, or attractor networks experience repeated writing, resulting in endurance stress [178]. Even volatile devices, though self-resetting, can degrade under high-frequency pulsing or sustained bias [179]. Endurance requirements therefore depend on both device physics and usage patterns: MVM during inference imposes low stress, whereas on-chip training or analog matrix-equation solving demands high endurance during iterative updates. Dynamic-switching applications, with inherently frequent state changes, generally impose the most stringent endurance constraints. Practical systems must budget write cycles, minimize redundant updates, and employ endurance-aware strategies such as write reduction, wear leveling, or hybrid retention.

Device variability and stochastic switching are double-edged. Uncontrolled variability undermines deterministic operations such as stateful logic or associative recall, yet controlled variability can enrich reservoir dynamics and provide intrinsic randomness for probabilistic inference [5]. Algorithmically, two strategies emerge: (1) suppress variability where determinism is critical through device screening, redundancy, or digital correction; and (2) exploit variability where randomness is beneficial through noise-aware training or stochastic sampling. When high precision is required, bit-parallel or bit-serial mappings are used, albeit with increased sequencing overhead and endurance cost [29].

Mapping large models onto finite arrays involves tiling, batching, and scheduling [42]. Architectures with reusable weights, such as CNNs, benefit from repeated matrix access, which amortizes DAC/ADC overhead and mitigates endurance stress. In contrast, models with frequent weight updates—such as online-trained RNNs or dynamically updated Transformer key–value caches—impose higher write demands and tighter timing constraints. GNNs and other sparse workloads exhibit irregular access patterns, often inefficient on dense crossbars, motivating hybrid sparse–dense or time-multiplexed designs. Bit-serial quantization can reduce per-device precision requirements but increases control complexity and latency [42,180]. Across the system stack, peripheral power and area often dominate: ADC/DAC resolution, amplifier linearity, and selector/driver overhead all contribute to overall trade-offs [29].

Effective deployment requires co-design across device, circuit, and algorithm levels. At the device–circuit interface, calibrated multi-step programming, verify-and-tune procedures, and selector integration remain essential to mitigate nonlinearity, variability, and IR-drop [29]. Dynamic-switching functionalities introduce additional challenges in timing, retention, reproducibility, and pulse fidelity [181]. For example, stateful logic depends on precise pulse timing and controlled SET/RESET probabilities [114]. Attractor networks require drift stability and tuned feedback gain [129]. Stochastic computing demands well-characterized switching-probability curves, low autocorrelation, and controlled bias [164]. STDP circuits need calibrated spike-pair protocols and symmetric, high-resolution updates [151]. Reservoir processors rely on matched time constants and appropriate masking or multiplexing [136]. At the array level, partitioning, local pre-compensation, and redundancy mitigate distortions from heterogeneity and IR-drop [42]. Architecturally, hybrid approaches are effective—using dense analog MVM for bulk linear algebra, paired with stochastic or temporal modules for task-specific dynamics [134]. Algorithmic remedies such as hardware-in-the-loop training, noise-aware optimization, regularization and preconditioning relax device constraints and improve end-to-end accuracy [75,82]. System-level strategies including wear leveling, periodic calibration, and mixed-precision accumulation help balance endurance, energy, and fidelity.

Static conductance and dynamic switching modalities are complementary and often interdependent. Static conductance enables stable, high-throughput analog computation, while dynamic switching extends functionality to stateful logic and temporal processing. Both rely on the same physical memristor substrate and thus share constraints of variability, endurance, and peripheral overhead—necessitating unified co-design. Ultimately, scalable memristive AI accelerators will depend on architectures that integrate both modalities seamlessly, assign each to its optimal computational role, and coordinate design across materials, circuits, and algorithms to balance precision, adaptability, and reliability.

6. Conclusions

Memristors offer two complementary hardware primitives—static conductance and dynamic switching—that together open new pathways for energy-efficient, low-latency on-device AI. Static conductance in dense crossbar arrays enables highly parallel matrix–vector multiplication and supports both digital in-memory arithmetic and closed-loop AMC topologies. These capabilities directly accelerate core linear-algebra workloads in modern networks, from fully connected and convolutional layers to transformers. Dynamic, volatile memristors provide fading memory and intrinsic nonlinearity. They enable temporal processing primitives such as reservoir computing, spiking networks with STDP, attractor dynamics, and hardware-native stochastic computation. Together, these device modalities permit compact implementations of both data-parallel and time-domain AI primitives.

Significant progress has been made at device, circuit, and system levels. Experimental demonstrations show viable MAC acceleration, one-step analog solvers, reservoir-based speech and biosignal processing, and on-line STDP learning in integrated arrays. At the same time, non-idealities remain the major barrier to deployment. Device variability, stochastic switching, endurance and retention limits, wire parasitics, and peripheral overhead constrain achievable accuracy, throughput, and energy efficiency.

Realizing practical memristor-based AI requires integrated solutions. We advocate coordinated device–circuit–algorithm co-design, hybrid analog–digital architectures that place each primitive where it is most effective, robust pulse and calibration strategies, and compiler toolchains for mapping algorithms to hardware. Standardized benchmarks and reproducible system demonstrations will be essential to quantify benefits. With these efforts, memristor technologies can move from compelling laboratory prototypes to scalable, application-ready accelerators that bring powerful AI capabilities to edge and embedded platforms.