ChipForm: Automated Constraint-Driven IC Layout Optimization via Reinforcement Learning

The automation of Integrated Circuit (IC) physical layout optimization remains a critical challenge, primarily due to the complex interplay between electrical and physical constraints. We propose ChipForm, a framework that reframes this task as a constraint-driven, reinforcement learning-guided graph optimization problem. Unlike perception-based approaches, ChipForm directly processes circuit netlists using a Hierarchical Graph Encoder (HGE) to extract features and predict timing, power, and density constraints. Subsequently, a Reinforcement Learning Placement Agent (RLPA) performs sequential cell placement, optimizing for minimal wirelength while explicitly satisfying these predicted constraints. A key contribution is a unified, end-to-end training strategy that jointly optimizes constraint prediction and placement policy. Extensive experiments on the CircuitNet benchmark demonstrate state-of-the-art performance: ChipForm achieves an 85.2% physical executability rate (DRC/LVS pass) and reduces constraint prediction errors (e.g., 0.11 OOD timing criticality error) compared to prior methods. Ablation studies confirm the necessity of each component, showing that explicit constraint prediction heads improve OOD generalization by 5.7% in executability, and the RL agent outperforms a greedy baseline by 3.9%. ChipForm thus provides a robust, data-driven approach for generating high-quality, manufacturable chip layouts directly from netlist specifications.