Submitted:
29 April 2025
Posted:
30 April 2025
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Abstract
Keywords:
1. Introduction
- Multiple Processing Cores: Some network devices have multiple CPU cores or processing units. P4 programs can be designed to distribute packet processing tasks across these cores to achieve parallelism. For example, one core might handle packet parsing, while another core handles packet forwarding.
- Parallel Pipelines: P4 allows the definition of multiple packet processing stages within a pipeline. These stages can be designed to operate in parallel, with each stage processing packets independently. For instance, one stage might perform access control checks while another stage performs packet routing.
- Hardware Offload: In some cases, P4 programs can be used to offload certain packet processing tasks to specialized hardware accelerators or programmable ASICs. These hardware components can operate in parallel with the CPU, further increasing packet processing efficiency.
- Load Balancing: P4 can be used to implement load balancing mechanisms, where incoming packets are distributed across multiple processing units or network paths, enabling parallel processing of packets.
1.1. Related Work
1.2. Contributions
- Investigated the overhead created due to the slow path utilisation of OvS and the performance variation in comparison to a P4 target switch. With more and more packets requiring processing using a controller, a network model that utilises a slow path approach such as OvS will potentially lead to an exponential growth in traffic congestion.
- Evaluated the performance of networks when SDN+P4 is employed rather than SDN+OvS. The evolution of 5G and beyond has led to the need to evaluate methods for reducing the delay at the core. Initialising programmability in the network has been shown to increase performance at the core. To the best of our knowledge, current literature does not evaluate the performance of the network when the control plane and data plane programmability (SDN+P4) is employed in comparison to the control plane (SDN+OvS) programmability.
- For a time-sensitive application with minimal latency requirements, reducing the delay at the core can be essential. For example, Vehicle-to-Vehicle (V2V) and Ultra Reliable Low Latency Communication (URLLC) applications. A solution, that processes packets in parallel as opposed to sequential processing in OvS, has been considered in this research and its effect on performance in applications. Our research has established that with the initialisation of SDN+P4 with parallel processing of packets, various applications have better performance in comparison to applications run over SDN+OvS.
- Evaluated the quality of applications and the effect SDN+P4 had on the network traffic of ICMP, TCP, UDP, SIP and CDN in comparison to SDN+OvS. The statistics such as increased bps and throughput, reduced delay jitter, packet loss, delay and buffering time have led to a higher quality of performance at the receiver’s end
1.3. Structure of the Paper
2. System Platforms
2.1. SDN Platform
2.2. Mininet
2.3. P4 Switch
3. Experimental Design
3.1. Network Topologies
3.2. Traffic Design
3.3. Tier-I—Single Type of Traffic Run
3.4. Tier-II—Multiple Types of Traffic Running Simultaneously
4. Results and Analysis of Tier-I Single Type of Traffic Run
4.1. Case Study 1—ICMP
4.2. Case Study 2—TCP

4.3. Case Study 3—UDP

4.4. Case Study 4- Content Delivery Network

5. Results and Analysis of Tier-II—Multiple Types of Traffic Running Simultaneously
5.1. Case Study 5—Mixed Type of Traffic over Grid Topology

5.2. Case Study 6—Simultaneous Run over the Internet Topology
6. Discussion

7. Conclusions
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| Traffic | Multi-Path Topology and Grid Topology |
Internet Topology |
| Client → Server | Client → Server | |
| ICMP | H1 → H5, H2 → H6, H3 → H7, H4 → H8 |
H1 → H21, H5 → H22, H9 → H23, H13 → H24, H17 → H25 |
| TCP | H1 → H5, H2 → H6, H3 → H7, H4 → H8 |
H2 → H26, H6 → H27, H10 → H28, H14 → H29, H18 → H30 |
| UDP | H1 → H5, H2 → H6, H3 → H7, H4 → H8 |
H3 → H31, H7 → H32, H11 → H33, H15 → H34, H19 → H35 |
| CDN | H1 → H8, H2 → H8, H3 → H8, H4 → H8 |
H4 → H36, H8 → H36, H12 → H36, H16 → H36, H20 → H36 |
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