A Survey of Machine and Deep Learning Techniques in Analog Integrated Circuit Layout Synthesis

1. Introduction

In recent decades, the integrated circuit (IC) industry has experienced remarkable growth, evolving into a multi-billion-dollar sector driven by the surging demand for consumer electronics, which depend heavily on sophisticated systems-on-a-chip (SoCs). While digital signal processing and memory components are essential for the functioning of these SoCs, analog interfaces like wireless communication circuits and sensors are equally critical for enabling interaction with the external world. Although electronic design automation (EDA) tools for digital and memory block design are well-established, the design and layout of analog circuits remain a challenging, error-prone task. With designers relying on traditional computer-aided design (CAD) tools, including schematic editors, simulators, and verification tools, in a repetitive, manual process. Nonetheless, tools and techniques to automate its design process have been vastly proposed by the analog EDA research community for more than four decades, still, there is no established automatic tool or flow in the industrial environment, resulting in a time-consuming and difficult-to-reuse design process. However, recent advances in machine and deep learning (M/DL) have opened new opportunities in the automation of the analog IC design flow, where part of the path has already been paved, such as in device, circuit and system-level modeling, automatic synthesis techniques or even testing [1,2,3,4].

This paper reviews the most recent M/DL efforts applied to automatic analog IC layout generation, which is the task of the analog design flow that both lays the devices out in the chip (i.e., placement), and after, interconnects them (i.e., routing). It is important to note that as analog IC design moved into modern deep nanometer technology nodes, the growing topological requirements, additional process design kit (PDK)’s rules, congestion, and parasitic structures that arise from the physical layout description are continuously defying existent EDA tools. In particular, layout parasitic structures and layout-dependent effects (LDEs) if not adequately weighted during layout design, have been proved to drive analog ICs from promising pre-layout performances to completely malfunction. Hence, their real impact can only be known after complete layout extraction and post-layout simulation, as illustrated in Figure 1. Still, this layout design flow suffers from expensive and time-consuming redesign iterations with limited feedback information to correct the problem. Layout generators powered by novel M/DL techniques are opening new perspectives for developing solutions that simultaneously incorporate legacy data or expert design insights in a manner that was not possible in the previous generations of EDA tools, and therefore, are covered in this review.

This paper is organized as follows: Section 2 presents the most recent advances in neural network-based and reinforcement learning (RL)-based placement; Section 3 shows the improvements on routers enhanced by routing probability maps generated by M/DL, and also, net ordering and track-assignment techniques; Section 4 discusses the preliminary developments on post-layout performance estimation; and, Section 5 summarizes the topics covered on this review.

2. Placement

The analog IC placement consists of determining the positions for the devices of a given circuit/system topology. The task is conducted taking simultaneously many requirements into consideration in order to reduce the unwanted impact of layout parasitic structures, process variations and different on-die operating conditions. Those requirements, which traditionally appear in the form of device symmetry, matching and proximity constraints, among others, allied to the multitude of possible device implementations, with different sizes and aspect ratios, make the analog placement task hard to automate. Furthermore, these constraints must be strictly satisfied while attempting to minimize several objectives, such as chip area or interconnect length estimates, as most of the parasitic effects and consequent performance degradation of the circuit post-layout and the attainable routing quality are set once a placement solution is fixed. For these reasons, automatic analog placement has been an intensive research topic in the research community [5,6].

2.1. A Summary of Traditional Automatic Approaches

Traditional approaches for automating analog IC placement can be categorized into three main types: (1) constrained optimization, where an optimization method, typically using simulated annealing (SA), is applied to adjust the positions of the devices either explicitly or implicitly, with the goal of minimizing specific performance metrics. In the explicit approach, where absolute coordinates are used, each device is defined by its position on a plane without a grid [7,8,9]. This method can represent all possible placements and is the most practical for enforcing topological constraints, as these can be directly implemented using the device coordinates. However, the algorithm must search through both feasible and infeasible solutions, since overlaps between devices may occur. In the implicit approach, where relative positions are employed, the optimizer modifies a structure that represents the layout, and a packing procedure then converts this relative representation into a complete floorplan, while preventing overlaps and ensuring that the necessary topological constraints are satisfied. In this case, the search space is restricted to feasible solutions only. However, implementing topological constraints can be more challenging, as each time the optimizer alters the structure, it must re-evaluate and adjust the layout to address any violations or fixes needed. These discrete operations complicate the original simplicity of relative representations, still notable implementations can be found for the: ordered tree (O-tree) [10], binary tree (B*-tree) [11,12,13], transitive closure graph (TCG) [14,15], hierarchical B*-tree [16], QB-Tree [17] and sequence-pair (SP) [18,19,20,21,22]. Both the explicit and implicit methods do not take into account any previously created layouts, meaning they do not utilize any legacy data; (2) retargeting from an existing design or template involves using the design patterns from a prior floorplan to recreate the same circuit topology, but with new device sizes or integration technology [23,24]. A generic template, independent of technology or specifications, can also be employed to represent these design patterns, with fast compaction techniques applied to produce the updated solution [25]; and (3) knowledge mining takes a different approach by using a collection of legacy layouts instead of just one. In this case, the generated solution doesn’t have to match a specific topology from the legacy data but can be derived from the design patterns of various sub-circuits identified in the library [26].

2.2. M/DL Advances: Neural Network-Based

A preliminary proposal for using M/DL in automating the placement of analog ICs was introduced in [27], where mean-field neural networks were utilized to represent planes with grids for device placement. The problem was framed as a network consisting of multiple parallel planes, one for each device in the circuit. Each plane’s dimensions matched the discrete space available for placing the devices. The grid's edges acted as neurons, and an active neuron indicated the bottom-left coordinate of a device corresponding to its plane. The model optimized an energy function, which penalized issues like device spacing, overlap, symmetry violations, proximity rule breaches, and out-of-bounds placements. These models were topology-dependent, and the discrete space structure makes the model's framework inherently reliant on the dimensions of the devised plane. On a different trail, artificial neural networks (ANNs) were employed to study the design patterns of thousands of validated placement solutions for a single topology [28]. These placements varied while still meeting symmetry and current-flow requirements, with the goal being to train the model to recognize and apply these design patterns to new size scenarios. The output of the network was the position of each of the circuit’s devices in an ℝ² plane, and it was trained to minimize the mean squared error (MSE) between the predicted floorplan and its corresponding solution from the training set. As shown in Figure 2, the model outputted three different floorplans, i.e., one for minimum area, minimum width and minimum height, when requested with a different set of design variables and cells’ physical details.

An improved approach can be found in DeepPlacer [29,30], which uses an ANN trained in a semi-supervised manner and evaluated with a topological constraint satisfaction loss function. Instead of comparing the predicted placements with legacy data, this method assesses whether the placements meet the specified constraints, encouraging new yet accurate behaviors. The study also introduced circuit topology encodings by embedding the topological constraints into the input layer of the ANN using directed graphs, as illustrated in Figure 3. This enabled the model to be applied to various circuit topologies, allowing for knowledge reuse across different designs. However, the model’s limitations include its inability to account for the data structure, restricting it to a fixed maximum number of devices. Additionally, the model's dependence on the order in which devices were fed into it made its real-world application challenging. To address the limitations of encoding circuit characteristics in the input layer, Graph2Seq [31] employed modern embedding methods and a fully unsupervised attention-based encoder-decoder model for automating the analog IC layout placement task. By using a graph-structured input, the model became independent of the device order and scalable, allowing it to handle circuits with more devices than those it was trained on. The graph structure represented placement constraints, not the circuit’s connections, meaning the netlist was not required. By focusing on placement constraints instead of netlist connections, the model decoupled the circuit’s electrical properties from its placement rules, making it adaptable to changes in technology without needing retraining. As the model was trained on ensuring compliance with clearly defined topological constraints, it no longer depended on validated legacy layout data. Lastly, the inclusion of a sequential decoder made the model independent of node identification, a common limitation on the number of devices that could be considered. While sequential models typically rely on order, the attention mechanism in this model allowed it to select the order autonomously, making it order-invariant.

In a different direction, Xu et al [32] proposed a conditional generative adversarial network (GAN) to automate the process of well design based on human expertise examples. The generator was trained to produce well patterns from images of legacy placements, where the use of patches of the layout image as the input/output data results in a model invariant to the number of devices. Later, that method was used to perform well-aware placement in [33].

2.3. M/DL Advances: Reinforcement Learning-Based

In [34], a reinforcement learning (RL) approach for FinFET analog placement design is proposed. There, during the initialization, the devices are distributed on the floorplan in a way that complies with FinFET technology rules, and then, the coordinates of each module (i.e., the environment state) are fed to the agent. During training, the agent chooses an action among moving up, down, left, right, and no move, to take for each device and the environment executes the actions, evaluating the newly generated layout in terms of design objectives, and therefore, providing a reward for the actions taken. The agent then updates the weights and biases of the policy implemented with a deep ANN. This update is made according to the reward that it was received from the environment. Consequently, instead of a greedy or random search to find the best location for each device within a placement problem, the agent learned to choose the best action for a given environment state, in order to achieve a higher reward. Experimental results showed that the trained model generated layouts that meet the design objectives more efficiently than greedy search. Similarly, following the RL path, in [35] the problem is framed as a Markov decision process (MDP), and RL is applied alone and in cooperation with SA. The underlying topological representation encoding the layout is a SP, and the RL is responsible for performing the SP moves that maximize the reward while accounting with an obstacle avoiding rectilinear Steiner tree algorithm to minimize interconnect length. In [36], the previous work is enhanced by combining relational graph convolutional neural networks (R-GCNs) and RL to create floorplans for a broader scope of analog circuit topologies. The R-GCN served as an encoder of the circuit, device and geometric constraints, and, provided that detailed information to the RL agent, which combined it with spatial encodings from a convolutional neural network (CNN) to determine the best shape and placement coordinates for each component.

In a slightly different direction, [37,38] focused on the next-generation high-resolution lithography technologies, where electron-beam lithography (EBL) is preferred for cost-effective mask manufacturing, despite suffering from the so called foggy effect. As a nanofabrication technique, EBL scans a substrate surface covered with a thin organic film (resist) using a tightly focused electron beam (exposure), even though the focused electron beam will pass through the resist, there are some electrons that deviate from the intended direction. To contour some of the negative effects of the scattered electrons, these works proposed placement mechanisms built over B*-tree topological representations, whose state update is controlled with an RL environment. These placement methodologies assisted by M/DL are summarized in Table 1.

3. Routing

Routing is a definitive process in IC layout design, where the exact conductor paths required to electrically connect all components of the circuit/system are formally drawn using different metallization layers. In the analog domain, it is widely recognized that the performance of circuits/systems is heavily influenced by the parasitic structures introduced during layout design. Therefore, analog routing has traditionally been a meticulous, handcrafted task, requiring a higher level of manual detail when compared to its digital counterpart, where EDA tools are fairly well developed. Contrasting to digital ICs, analog circuits typically have a smaller number of nets to be routed, but each is carefully drawn due to the specific constraints and prerequisites involved. For this reason, various automation tools for analog routing have been extensively proposed by the research community for over four decades [39]. It is also important to highlight that since routing is one of the final stages in the IC design flow, the achievable routing quality is largely determined by the preceding layout design tasks, particularly placement. Several design strategies can minimize the required wiring during device- or block-level placement, such as interdigitated and common-centroid configurations or device merging. Furthermore, the exact location of devices and its terminals on the floorplan plays a crucial role in determining the success of the routing task. As overviewed in the previous Section, automatic placement strategies have been thoroughly explored by the EDA community, and the most-recent solutions have been continuously improved to accommodate a variety of layout styles and restrictions.

3.1. A Summary of Traditional Automatic Approaches

Conventional routing methods can be categorized into five main groups: (1) procedural routers, which generate routing solutions through hardcoded scripts. These routers consistently produce the same output for the same input set, and their ability to adapt to new designs is limited. They are ideal when complete control over the routing process is required, though they are time-intensive to develop and maintain. However, they are efficient in generating solutions quickly. Notable examples include BALLISTIC [40] or MSL [41], and more recently, BAG2 [42] and LAYGO [43]; (2) template-based routers, which use a technology-independent template to represent the routing process, generating the final solution when new device sizes and technology data are inputted. These routers are especially useful when migrating legacy layouts to different integration nodes or making design adjustments, as seen in IPRAIL [44], LAYGEN [45] or LDS [46]; (3) digitally-inspired routers, such as those found in ILAC [47], ALADIN [48] or ALG [49], which rely on channel routing techniques adapted from the successful methods used in the digital EDA domain; (4) sequential path-finding routers or area routers, where an algorithm is used to draw wires over a fine or coarse grid to connect different terminals of a net while avoiding obstacles. While these routers incorporate a range of routing techniques as constraints, they heavily rely on heuristics like rip-up and reroute to resolve conflicts between different nets or even wires within the same net. Supporting algorithms can be based on Lee’s maze router, as found on ROAD [50] and ILAC [51], or on line-expansion-style routers, as implemented on ANAGRAM II [52], or more recently, on MAGICAL [53] framework; and finally (5) concurrent routers, with different techniques that attempted to handle all the wires of all the nets at once, pursuing a global optimum. This was achieved by coding the complete routing of a circuit into an integer linear programming [54] problem, or by using optimization-based techniques, such as evolutionary-based tools LAYGEN II [55] and AIDA-L [56,57], where a chromosome is used to encode the representation of all wires of all net required in a circuit. The candidate chromosomes, i.e., different routing solutions, are then evaluated by internal design-rule and layout-versus-schematic checkers. An extensive review of traditional automatic routing approaches can be found in [39].

3.2. M/DL Advances

Recently, M/DL has begun to be applied to analog IC routing. The first reported method was GeniusRoute [58], which extracts knowledge from a collection of legacy layouts and used it to assist an area router. During the pre-processing of training data, placement and routing are transformed into 2-D images, from which relevant routing information is extracted. For each data sample, the pins of the entire design and the pins of a specific net are mapped into two distinct 64×64 channels. These channels are then utilized in a two-step training process, where an ANN is first used as a variational autoencoder (VAE) in an unsupervised training manner, followed by supervised decoder training. The routing mechanism behind GeniusRoute relies on the classic A* pathfinding algorithm, which is enhanced by the model’s predictions to create a routing probability map that guided the search process. In the A* cost function a routing guidance component composed of two parts is used: a penalty for violating the guidance provided by the model, and a penalty for routing in the probability region of other nets. Traditional rip-up and reroute techniques are still used; however, the legacy design patterns will be present in the automatically generated routing solutions. Taking one step further in the probability map generation capabilities, Peneda et al. [59] applied CNN-based approach, but focusing on solving single-net routing problems while leveraging routing data that contained global optimum solutions for the multi-net problem. This way, it was able to provide probability maps of a specific net but aware of a multi-net routing context. The inputs to the CNN model were the devices’ placement and its terminals’ locations in a 256×256 image format, as illustrated on Figure 4.

In another approach, an attention-guided RL model was used to address the track-assignment issue in detailed routing [60]. This algorithm was designed to integrate design rules into the track-assignment process, where the model identified the optimal order for the set of device pairs to be routed, ensuring that the overall solution quality is optimized. In [61], the training of the RL model was guided by previous solutions, utilizing data from earlier results. Both approaches offered nearly 100× faster runtime compared to a basic scheduler based on an evolutionary algorithm, while still producing solutions with similar quality. In [62] RL is used to guide a custom mixed-signal detailed routing framework capable of handling design constraints and design rules for FinFET technologies. First, the routing solutions of each net are transformed into a heterogeneous graph representation. Afterwards, an initialization process is executed to set the input features of all vertices depending on their path-matching constraints. After the graph construction, two main phases are executed: RL policy learning, which samples sequences of observations, actions and the corresponding rewards for efficient data collection, training a RL policy maximizing reward; and afterwards, RL-guided rip-up and re-routing, which integrates the previously trained RL policies to determine most suitable rip-up and reroute sequences to guide a detailed routing algorithm. Ultimately, DPRoute [63] utilized multi-agent deep RL to optimize routing schedules between nets and addressed the net ordering issue. In this approach, each net was treated as an agent, which should take into account the actions of other agents while making decisions to avoid routing conflicts. In contrast to earlier tools focused on solving block or system-level routing, DPRoute is specifically designed for complex package routing challenges. It has been shown to reduce design violations and packaging wirelength when compared to traditional non-M/DL packaging routing algorithms. A summary of these initial routing techniques assisted by M/DL is provided in Table 2.

4. Post-Layout Performance Prediction

In recent years, layout-aware optimization of ICs operating in the analog spectrum became a reality [39]. However, since this has been usually achieved through full layout generation, layout extraction and post-layout simulation inside an automatic sizing process, the optimization times required have escalated, resulting in weeks of computational processing for a single topology even in modern workstations. Therefore, post-layout performance regressors have become essential in modern analog IC design optimization [64], as they will provide the means to bypass time-consuming post-layout extraction and simulation, ultimately learning the underlying relations between layout parasitic structures/LDEs and the functional behavior of the circuits/systems.

4.1. Traditional Performance-Driven Layout Generation Tools

Before the establishment of layout-aware synthesis tools and the arrival of advanced M/DL to EDA tools tailored for analog IC layout design, some tools attempted to minimize the gap between pre- and post-layout performance by performing a pre-layout sensitivity analysis of the circuit performances. For example, in [65], the result of the sensitivity analysis was used to generate a set of placement bounds (i.e., placement constraints), that were then used to constrain the automatic placement generation procedure. In [66,67] a direct performance-driven approach was taken instead, where the product of the sensitivity analysis was used to create linear equations that correlated the distance between devices and the degradation of different performance characteristics, e.g., gain or bandwidth, and quantified in the fitness function that was used to optimize other floorplan characteristics such as area or estimated wirelength. More recently, [68] replaced the linear correlations between devices’ distance and post-placement performance by utilizing performance regressors previously built from approximated data sampled from a pseudo-extracted netlist (i.e., not from simulation data). In a different direction, PEDefer [69] incorporated pseudo-post simulation during the selection of the previously extracted subcircuits. However, a library of very specific legacy data had to be available before synthesis.

4.2. Direct Transfer Learning from Pre to Post-Layout

Since pre-layout performance regressors naturally utilize the sizing design variables (widths, lengths, number of fingers, etc.) as features (the model’s inputs), some works have very recently attempted to perform transfer learning from pre to post-layout [70,71,72,73]. What all these works had in common is the update made in the pre-layout models, previously trained on abundant data, with a few post-layout samples. When compared with a random initialization method of the post-layout performance regressor model, fine-tuning achieved superior results after only a few backtracking iterations. This allowed the post-layout models to adaptively preserve useful model weights learned from the pre-layout domain, and modify others to meet the specific parasitic structures added to the circuit due to the layout masks. However, a major drawback it that the layouts used to produce post-layout data must be extremely regular, as no layout implementation details are provided at the input layer of the transferred models, only sizing-related parameters.

4.3. M/DL Advances: Classification-Based Approaches

Since layout requires that new dimensionalities are considered for performance estimation, a classification-based approach for evaluating the floorplan quality was introduced in [74,75]. These works introduced a classification-based approach for evaluating the floorplan quality, leveraging M/DL for feature extraction from layout images, and its workflow consisted of: (1) feature extraction, where the layout is decomposed into subcircuits (e.g., differential pairs, bias networks, etc.). Each component was represented as a grayscale image, encoding spatial placement relationships; (2) convolutional neural network, employing a 3D model where multiple layout feature maps are stacked along the depth axis. This allowed the model to capture the spatial dependencies between subcircuits; and (3) transfer learning for generalization, by pre-training the model on a large dataset and then fine-tuning it on smaller datasets for new circuits. However, the classification output follows a percentile-based threshold, with floorplans classified as “good” those being on the top 75% of expected performance, and “bad” floorplans on the bottom 25%. In a slightly different direction but maintaining on the classification approach, BagNet [76] was proposed which contained three main components for a layout-aware sizing flow: evolutionary algorithm to propose candidate sizing solutions; the BAG tool generating the layout for each candidate sizing; and, an ANN model acting as an oracle. The oracle learned to compare two different solutions in terms of their design variables, and selected one as the most promising solution in terms of post-layout functional behavior. It allows the framework to be more efficient, avoiding several extractions and post-layout simulations.

4.3. M/DL Advances: Regression-Based Approaches

Focused on numerical performance prediction, dropping the subjective “good/bad” classification, in [77] post-layout performance estimation is performed, where net weights are considered as input parameters of the regression model, and Bayesian optimization (BO) is utilized to optimize performance with respect to these net weights, improving the layout generation. Very recently, on Ponderous [78], a performance-driven analog IC placement optimizer, integrating post-layout performance regression via ML models, was proposed. The input features to the ML models were the device sizing and the (x, y) placement coordinates of each device in the layout, with principal component analysis being used to reduce the dimensionality of input feature vector. The ML regressors based on extremely randomized trees output the post-placement performances of interest quantitatively, bypassing extraction and simulation, while still providing accurate values to guide optimization process, as schematized in Figure 5. While [77,78] used net weights and (x, y) placement coordinates, respectively, to provide some layout-related data to the M/DL models, these approaches are harder to escalate. To contour that aspect, [79] exploited convolutional VAEs for feature extraction, ensuring that the approach remains inherently technology-independent, while avoiding the need for an explicit sizing/placement coordinates data to be inputted to the model, but instead, implicitly, via images. When pipelined with an ensemble of multi-layer perceptrons (MLPs), precise quantitative performance prediction was achieved for large amounts of data synthetically generated by automatic tools. In [80] the CNN path to predict post-layout performance figures was also taken, by focusing on developing a reliable method for offset prediction of several differential amplifiers.

Figure 5. Performance regression pipeline used to bypass off-the-shelf extraction and simulation in an automatic placement methodology (adapted from [78]).

Figure 5. Performance regression pipeline used to bypass off-the-shelf extraction and simulation in an automatic placement methodology (adapted from [78]).

Table 3. Summary of the M/DL Advances for analog Post-Layout Performance Prediction.

Tool	Year	Key Specification	Tech.	Base Code
BagNet [76]	2019	ANN model acting as an oracle to select the most promising solution	45nm	n/s
Liu [77]	2020	Net weights used as layout-related data and Bayesian optimization applied to optimize them	40nm	C++ & Python
Chang [75]	2023	CNN used to classify floorplan solutions as “good”/“bad”	n/s	n/s
Wang [72]	2024	Transfer learning from pre- to post-layout within an evolutionary algorithm-based synthesis	130-180nm	n/s
Li [73]	2024	Transfer learning from pre- to post-layout within RL-based synthesis	130-180nm	Python
Ponderous [78]	2024	Post-placement performance regression pipeline using (x, y) placement coordinates	65nm	Java & Python
Almeida [79]	2025	Convolutional VAEs and an ensemble of MLPs to estimate post-placement performance	65nm	Python

n/s – not specified.

Table 3. Summary of the M/DL Advances for analog Post-Layout Performance Prediction.

Tool	Year	Key Specification	Tech.	Base Code
BagNet [76]	2019	ANN model acting as an oracle to select the most promising solution	45nm	n/s
Liu [77]	2020	Net weights used as layout-related data and Bayesian optimization applied to optimize them	40nm	C++ & Python
Chang [75]	2023	CNN used to classify floorplan solutions as “good”/“bad”	n/s	n/s
Wang [72]	2024	Transfer learning from pre- to post-layout within an evolutionary algorithm-based synthesis	130-180nm	n/s
Li [73]	2024	Transfer learning from pre- to post-layout within RL-based synthesis	130-180nm	Python
Ponderous [78]	2024	Post-placement performance regression pipeline using (x, y) placement coordinates	65nm	Java & Python
Almeida [79]	2025	Convolutional VAEs and an ensemble of MLPs to estimate post-placement performance	65nm	Python

n/s – not specified.