On the Realization of “Dead Time” in a Synchronous Step-Down Converter

1. Introduction

The main issues in the design of DC/DC converters are presented in [1]. The difference between continuous and discontinuous current mode through the inductance is discussed for example in [2]. Typically, the synchronous step-down converter is implemented with two N-channel MOSFETs [3]. Issues related to the efficiency of such a converter are considered, for example, in [4,5,6,7]. The requirements for controlling MOSFETs are considered in many scientific works, such as [8,9,10,11,12,13]. In cases where the supply voltage does not exceed the maximum allowable gate-source voltage of a P-channel MOSFET, the upper N-channel transistor in the synchronous buck converter can be replaced by a P-channel transistor. This provides certain advantages in terms of controlling both transistors. It can be implemented by a single driver with push-pull output as shown in Figure 1. In this way, some additional elements are avoided to provide the control voltage of the upper transistor in case it is also N-channel – capacitor, diode and additional circuits [14]. However, it should be noted that in the proposed control in Figure 1, one of the two transistors is always on, while in the case of two N-channel transistors, both can be turned off under certain circumstances. This is a known disadvantage of the variant considered in this study, which is suitable, for example, when charging low-power energy storage elements - batteries, ultracapacitors. In this case, the constant current regulation and voltage limitation can be carried out, and when the maximum charging voltage is reached, the electronic regulator for this voltage remains to work, i.e. both transistors can be switched. Issues related to regulation and the rest of the control system are not the subject of consideration in this research. The charging circuits of the input capacitances of the two transistors is presented on Figure 1 (red lines) and the discharge circuits (blue lines). The additional elements to the gates of the transistors (the two resistors and the Schottky diode) are known and often recommended. Through these circuits, the so-called “dead time” is implemented when controlling the transistors. The goal is to turn one transistor on with a certain delay compared to turning the other off. This problem is known and also exists in other converters using phase leg transistors [15]. Different methods for realization “dead time” are known [16,17,18,19,20]. For the circuit of a synchronous converter using two N-channel MOSFETs, controllers in an integrated circuit are proposed, containing different methods for “dead time” realization [21,22]. The present work focuses on the realization with the circuits shown in Figure 1. The operating principle is as follows:

At a low level at the driver output (the lower transistor at its output is turned on), the input capacitance of the lower N-channel transistor is discharged through the diode $D_1$ and the driver output. At the same time, the input capacitance of the upper P-channel transistor is charged through the resistor $R_3$ to a voltage approximately equal to the supply +U (the difference is due to the voltage on the transistor at the driver output). At a high level at the driver output (the upper transistor at its output is turned on), the input capacitance of the upper P-channel transistor is discharged through the diode $D_2$ and the driver output. At the same time, the input capacitance of the lower N-channel transistor is charged through the resistor $R_1$ to a voltage approximately equal to the supply +U (the difference is due to the voltage on the transistor at the driver output). Since the charging of the input capacitances occurs through a resistor, the idea is to change its value and the charging time constant to change the turn-on delay time. It can be larger than that during turn-off, because the capacitance discharge occurs through the low-resistance Schottky diode [23].

In the literature known to the authors no methodology for sizing these circuits is described, especially with regard to the problem described below. This problem may occur in low-power converters, where the input power sources are small photovoltaics, piezoelectric elements, etc. In these cases, the transistors used are low-power. Characteristic features of low-power MOSFETs are the low threshold voltage $U_{th}$ (usually 0.7 – 1.5V) and the small value of the input capacitance $C_{iss}$ (usually tens to hundreds of pF). When controlling power MOSFETs, the described problem could not arise, since their threshold voltage is high (usually above 4.5V), and their input capacitance is larger (up to several tens of nF).

Description of the problem: When controlling the transistors in the manner shown in Figure 1, the authors observed the oscillograms shown in Figure 2 and Figure 3. The supply voltage of the converter is 3.3V. In Figure 2 - CH2, a steep trailing front is observed in the voltage of the drains of both transistors (point A – Figure 1), i.e. the lower transistor turns on very quickly. At the same moment, a sharp decrease is observed in the supply voltage on CH1. These are signs of simultaneous conduction of both transistors, i.e. a single-arm short circuit. From CH1 in Figure 3, it can be seen that at the same moment in time, the gate-source voltage of the lower transistor increases steeply, and it has been established that the rate of increase is not affected by a change in the value of the resistor R1 from Figure 1. This prompted a more detailed study of these circuits, described below.

2. Mathematical Descriptions and Study

Essential to the solution of the described question is the consideration of the influence of the Schottky diode capacitance when applying a signal to turn on the transistor. The study was carried out using the circuit shown in Figure 4, where the Schottky diode capacitance $C_j$ and the input capacitance of the transistor $C_{iss}$are added to the elements $D_1, R_1, R_2$existing in Figure 1. The equivalent circuit for mathematical description is presented in Figure 5.

It is assumed that the input voltage is increased stepwise to a value of 1 (single input pulse) $u_{in}=1$ and the change in the output voltage $u_{GS}$, which is the gate-source voltage of the transistor, is examined.

The expressions for the impedances from the circuit on Figure 5 in operator form are:

$$Z_1\left(s\right)={\displaystyle \frac{R_1}{1+s.R_1.C_1}};Z_2\left(s\right)={\displaystyle \frac{R_2}{1+s.R_2.C_2}}$$

(1)

For a single input, the output voltage has the form:

$$u_{GS}\left(s\right)={\displaystyle \frac{1}{s}}.{\displaystyle \frac{Z_2\left(s\right)}{Z_1\left(s\right)+Z_2\left(s\right)}}$$

(2)

It can be represented also:

$$u_{GS}\left(s\right)={\displaystyle \frac{A}{a+s}}+{\displaystyle \frac{B}{s\left(a+s\right)}}$$

(3)

where,

$$A={\displaystyle \frac{C_1}{C_1+C_2}}$$

(4)

$$B={\displaystyle \frac{R_2}{R_1+R_2}}$$

$$a={\displaystyle \frac{1}{\tau }}$$

$$\tau ={\displaystyle \frac{R_1.R_2.\left(C_1+C_2\right)}{R_1+R_2}}$$

When switching from Laplace form to the original, the change in output voltage over time is obtained:

$$u_{GS}\left(t\right)={A.e}^{-{\displaystyle \frac{t}{\tau }}}+B.\left(1-e^{-{\displaystyle \frac{t}{\tau }}}\right)$$

(5)

Figure 5 presents the two terms of expression (5) – the first with a blue line, the second – with a green line, and their sum – with a red line.

From Figure 6 it can be seen that the output voltage $u_{GS}$, which is the gate-source voltage of the transistor, has a sharp increase at the initial moment, which depends on the ratio of the two capacitances $C_1$ (the capacitance of the Schottky diode) and $C_2$ (the input capacitance of the MOSFET). For example, if $C_2\gg C_1$the value of the initial increase will be of a negligible value. If the two capacitances are equal, this value will be equal to half the value of the input voltage. However, if, $C_1\gg C_2$ the initial increase may be close to the value of the input voltage. This is the effect that is observed in the upper oscillogram of Figure 3. The problem is that depending on the ratio of the two capacitances, the value of the initial increase may be greater than the value of the threshold voltage $U_{th}$ of the transistor. In such a situation, “dead time” is not realized and the effect described in the introduction is observed.

Formula (5) can be used to determine the value of the “dead time” depending on the value of the resistor $R_1$ at known other values. For this purpose, it is presented in the form:

$$u_{GS}\left(t\right)={\left(A-B\right)e}^{-{\displaystyle \frac{t}{\tau }}}+B$$

(6)

When replacing $\mathit{t}={\mathit{t}}_{\mathit{d}}$ and ${\mathit{u}}_{\mathit{G}\mathit{S}}\left({\mathit{t}}_{\mathit{d}}\right)={\mathit{U}}_{\mathit{t}\mathit{h}}$ the expression is obtained:

$${\mathit{t}}_{\mathit{d}}=\mathit{\tau }.\mathit{l}\mathit{n}{\displaystyle \frac{\mathit{A}-\mathit{B}}{{\mathit{U}}_{\mathit{t}\mathit{h}}-\mathit{B}}}$$

(7)

By substituting in (7) the quantities from formula (4) we get:

$$t_d={\displaystyle \frac{R_1.R_{2.}\left(C_1+C_2\right)}{R_1+R_2}}.ln{\displaystyle \frac{\frac{C_1}{C_1+C_2}-\frac{R_2}{R_1+R_2}}{U_{th}-\frac{R_2}{R_1+R_2}}}$$

(8)

Because dependencies were derived at unit input, then the value of $U_{th}$ should be set in units relative to the maximum value of the driver's output voltage. So, for example, if it is 3V and the threshold voltage is 1.8V, in formula (8) for $U_{th}$ value 0.6 should be substituted.

In formula (8), the capacitance values are known from the reference data for the selected elements – Schottky diode, MOSFET and Zener diode parallel to the gate-source transition. The value of resistor $R_2$ is usually 10K. It remains for different values of $R_1$ to calculate the value of $t_d$ and choose the appropriate value of the resistor.

So, for example, for variant 4 of table 1 considered below, the values are as follows: $C_1=140pF$; $C_2=365pF$; $R_2=10K$. With a minimum threshold voltage of 1V for the MOSFET and an output voltage from the driver of 3V in formula (8) is placed $U_{th}={\displaystyle \frac{1}{3}}\approx 0.33$. After calculation at resistor value $R_1=500\mathsf{\Omega }$ a value is obtained for $t_d$ 111 ns.

A computer simulation was performed using models of real diodes and transistors. The results are shown and commented below.

Variant 1 – Schottky diode 1N5819 with a capacitance of 150 pF [24], input capacitance of the transistor 150 pF. The input signal has a maximum value of 5V. The simulation scheme and the results are shown on Figure 7.

It can be seen that when a signal is applied to turn on, the initial peak of the output voltage is 2.5 V in accordance with the coefficient A from Figure 6. When switched off, an initial retention of about 0.3 V (the voltage across the switched-on Schottky diode) is observed. It is clear that with such a combination, the realization of dead time will not be obtained for transistors with a threshold voltage below 2.5 V.

Variant 2 - Schottky diode 1N5819 with a capacitance of 150 pF [24], input capacitance of the transistor 500 pF. The input signal has a maximum value of 5V. The simulation scheme and the results are shown on Figure 8.

It can be seen, when a signal is applied to turn on, the initial peak of the output voltage is approximately 1V in accordance with the coefficient A from Figure 6. When switched off, an initial retention of about 0.3 V (the voltage across the switched-on Schottky diode) is observed. It is clear that with such a combination, the realization of “dead time” will not be obtained for transistors with a threshold voltage below 1V. When the input capacitance of the transistor increases, the initial jump of the gate-source voltage decreases.

Variant 3 – Silicon diode 1N4148 with a capacitance of 3 pF [25], input capacitance of the transistor 500 pF. The input signal has a maximum value of 5V. The simulation scheme and the results are presented on Figure 9. This option was chosen because pulse diodes with a PN junction are characterized by significantly smaller capacitance values.

This variant corresponds to the condition $C_2\gg C_1$It can be seen that when a signal is applied to turn on, the initial peak of the output voltage is negligibly small in accordance with the coefficient A - Figure 6. It is clear that with such a combination the implementation of “dead time” when turning on the lower transistor will be the easiest even at low threshold voltages. When turning off, an initial hold of a value of about 0.7 V (the voltage on the switched-on diode) is observed. However, this is unpleasant, since at the same moment a signal is applied to turn on the upper transistor of the synchronous converter and at threshold voltages of the lower one about 0.7 V the latter may remain on for a short time. This would make it difficult to implement “dead time” when turning on the upper transistor. For this reason, the authors recommend using Schottky diodes, as in the scheme on Figure 1.

Variant 4 – Connecting a zener diode in parallel with the gate-source junction of the transistor. The diode has protective functions and are described in the literature [8,9]. The schematic diagram together with the capacitances is shown on Figure 10. - Schottky diode 1N5819 with a capacitance of 150 pF [24], input capacitance of the transistor 500 pF, zener diode BZX84C5V6 SMD with a capacitance of 200 pF [26]. The input signal has a maximum value of 5V. The simulation scheme and the results are shown on Figure 11.

This variant differs from variant 2 only in the inclusion of the zener diode. From the comparison of the timing diagrams on Figure 11 with those on Figure 8, it is seen that the initial peak is reduced to about 0.9 V, which would facilitate the implementation of “dead time” for transistors with a threshold voltage above 1V. In addition to the protective function, the authors recommend placing a zener diode also from the point of view of the issue considered in this article.

3. Experimental

The initially implemented variant for the lower transistor on Figure 1 is the following: transistor BSS214N with capacitance $C_{iss}=107pF$ and threshold voltage $U_{th}=0.7V$ [27] and Schottky diode SS34 with capacitance $C_j=1nF÷500pF$ [28]. The oscillograms shown on Figure 2 and Figure 3 correspond to this variant. From the previous consideration, it is clear that this variant is unsuitable. Table 1 shows various possible variants for implementation - combinations of Schottky diodes and transistors with or without a zener diode. Those shown in red are unsuitable, the one in yellow is not preferable, since the results are close to the limit. From the point of view of “dead time”, variants 4, 5 and 6 are suitable - shown in green. Variants 5 and 6 are not preferred due to the considerations expressed when commenting on the results in Figure 9. The preferred implementation variant is 4, shown in blue in the first column of Table 1. It uses a Schottky diode SS14 with a significantly smaller capacitance than SS34 [29].

The last three variants from Table 1 were evaluated from the following point of view: When turning on the upper transistor from Figure 1 and increasing the voltage in point A, through the feedback capacitance $C_{rss}$ of the lower transistor, its gate-source capacitance is charged (Miller effect) [30]. Shortly before this (to ensure the “dead time”) there is a low level at the driver output. In this situation, due to the feedback, the input capacitance would be charged to a voltage equal to the sum of the drop on the Schottky diode (or the pulse diode with a PN junction) and the voltage on the lower transistor of the driver. This sum of voltages must remain less than the threshold voltage of the lower transistor, otherwise it is possible to turn it on as well. With a sharp increase in the voltage at point A, the consideration made in the previous part can be applied. The results from Table 2 show that from such a point of view, variants 5 and 6 are borderline (shown in yellow). Variant 4 (in green) is also suitable for this consideration.

After the implementation assessment, variant 4 was chosen, and the part of the board corresponding to the scheme under consideration is shown in Figure 12. All electronic elements correspond to this variant 4.

Schottky diodes ${\mathit{D}}_6$ and ${\mathit{D}}_7$ are SS14 and correspond to ${\mathit{D}}_2$ and ${\mathit{D}}_1$ in Figure 1. Resistors ${\mathit{R}}_{10}$ and ${\mathit{R}}_{13}$ consist of two parallel-connected resistors with a value of 1K and correspond to ${\mathit{R}}_3$ and ${\mathit{R}}_1$ in Figure 1. Resistors ${\mathit{R}}_9$ and ${\mathit{R}}_{10}$ have a value of 10K and correspond to ${\mathit{R}}_4$ and ${\mathit{R}}_2$ in Figure 1. zener diodes BZM55C5V1 are soldered to these resistors. The transistor M1 (P-channel) is BSP250. The transistor M2 (N-channel) is UT6402G. The two drains pins are connected externally together with the left terminal of the inductance in the diagram of Figure 1 (point A – Figure 1).

Figure 13 and Figure 14 show the recorded oscillograms. The operating frequency of the converter is 17 kHz, and the supply voltage is 3.3 V.

From CN2 on Figure 13, the gradual increase in the gate-emitter voltage of the N-channel transistor when turned on (to realize “dead time” when turning off the P-channel transistor) and a rapid decrease (to realize “dead time” when turning on the P-channel transistor) are observed.

From CN2 in Figure 14, it can be seen that there are no short-term dips in the supply voltage both during switching on and during switching off of the N-channel transistor. The measured current, consumed by the power source in this case is significantly less than that in the case of Figure 2. These are proofs of correct implementation of dead time according to the scheme of Figure 10 for the two transistors of the synchronous step-down converter.

4. Conclusions

The article presents the results of the study of a synchronous step-down converter implemented with P-channel and N-channel MOSFET. The realization of “dead time” with external elements when controlled by a driver with push-pull output is considered. Main attention is paid to the influence of the Schottky diode capacitance. The main conclusions are as follows:

• It is recommended to implement the external circuits to the gate of the transistor according to the scheme in Figure 10.
• When designing “dead time’ circuits, it is necessary that the Schottky diode capacitance be significantly smaller than the input capacitance of the transistor.
• Based on formula (5) and Figure 6, the compliance with the threshold voltage of the MOSFET must also be checked.
• It is not recommended to use a pulse diode with a PN junction instead of a Schottky diode due to possible parasitic charging of the input capacitance of the transistor through the feedback capacitance when the upper transistor is turned off and possible reaching the threshold voltage of the lower.
• It is recommended to include zener diodes in parallel with the gate-source junction of the transistors with the lowest possible reference voltage, but greater than the maximum threshold (zener diodes with lower reference voltage have greater capacitance). In addition to their protective function, these diodes also facilitate the realization of “dead time”.
• Formula (8) can be used to determine the value of the dead time $t_d$ at different values of the resistor $R_1$ and known values of the other quantities as described above.

The considerations and conclusions presented in this article refer not only to the diagram in Figure 1. They can be applied in all cases of implementation of dead time according to the scheme of Figure 10.