Conclusive Algorithm with Kink Effects for Fitting 3-D FinFET and Planar MOSFET Characteristic Curves

1. Introduction

Short channel effects result in unwanted noticeable leakage current, which is successfully suppressed through halo-implant or pocket implant on, e.g., planar MOSFET with 0.18μm or 90nm long channel, in which the gate caps on the top of the channel. Unfortunately, the implant process fails to effectively stop leakage current on, e.g., 20nm any longer. Instead, FinFET sustains the capability of suppression of outrageously leaky current by using a gate-over-90%-surrounding 3-D slim channel for down to 3nm process technique. GAAFET replaces the role of FinFET by gate-completely-surrounding the whole channel for 2nm process technique. For one thing, the suppression of leakage current is due to creating depletion region in thin epi-taxial silicon which blocks the leakage current by building up a hill high potential barrier. However, the trend of shorter channels promotes the speed of transmitting signals via carriers and makes artificial intelligence (AI) possible, where the non-linear problem-sorting deep neural network (DNN), image-sorting convolution neural network (CNN), and speech-recognizing recurrent neural network (RNN) become available. [1,2,3,4,5,6]

Epi-silicon is tremendously important for its nearly identically flawless pure silicon that allows no enhancement of leakage current. Thicker epi-silicon film, such as tens of μm or a hundred μm, even plays roles of power discrete with high sustainable voltage bias. Thinner epi-silicon, such as 10 μm, is expected on integrated circuit (IC), though. Looking like an emerging 3-D “I” with two ends of Source and Drain, FinFET uses Gate poly-silicon crossing over the channel to conduct current in between Source and Drain by applying a bias to the Gate. Simultaneously, the Gate bias depletes the whole slim channel and builds up a barrier that blocks the leakage current. The achievable function of the process is mostly due to the good conformality (step coverage) of chemical vapor deposition, in which SiH₄ (silane) is controlled at a chosen flow rate and the ambient is sustained at an appropriate temperature and at certain pressure to achieve a good deposition rate in kinetic regime.[7,8,9,10,11,12,13,14,15]

Somehow, the electrical performances of transistors are mainly manifested in current-versus-voltage characteristic curves. Those curves are necessarily parameter-extracted in the model, which is useful to develop circuit design. Therefore, the as measured I-V curves are thought to be well fitted to determine predominant parameters. In this study, an advisable algorithm using the “modified” conventional I-V characteristic curve formula along with kink effects generates fitting data to minimize the deviations from the measured ones. Promising are the as determined parameters, such as the threshold voltage (V_th), lambda (λ), and k_N which is mainly proportional to the mobility.

2. Preparation, Measurements Fitting Algorithm

2.1. Preparation and Measurement of NFinFET

The grown 10μm epi-silicon layer is ionic dry etched to form a 3-dimensional 120nm wide and corresponding 9 times high fin channel. With two ends as Source and Drain, the whole epi-silicon channel looks like a letter “I”, which is followed with a grown thin gate oxide. The slim channel of “I” is then covered with arsenic heavily doped poly-silicon, called Gate. As the Gate is applied with a positive bias, the channel surrounded with Gate is then almost completely depleted, and right underneath the gate oxide, about 200 angstroms [16] p-type silicon gets strongly inversed into effectively 90nm long n-type silicon. The I_DS versus V_DS is then measured at various Gate biases.

2.2. Fitting I_DS-V_DS and I_DS-V_GS

The two-regime conventional formulas for FinFET and MOSFET transistors have to be modified as followed:

$$\begin{array}{c}{I}_{DS}(triode)=k_N[(V_{GS}-V_{th})V_{DS}-\frac{V_{DS}^2}{2}](1+\lambda V_{DS})\\ -\alpha \exp [-\beta {(\mathrm{V}}_{\mathrm{DS}}-\chi {)}^2]\end{array}$$

(1)

and

$$\begin{array}{c}{I}_{DS}(saturation)=k_N[\frac{{(V_{GS}-V_{th})}^2}{2}](1+\lambda V_{DS})\\ -\alpha \exp [-\beta {(\mathrm{V}}_{\mathrm{DS}}-\chi {)}^2]\\ \mathit{where}{k}_N=\frac{C_{ox}(1)W_{eff}\mu }{L_o},\lambda =\frac{1}{\left|V_A\right|},and(\chi ,\alpha )\equiv (V_{DS\_kink},I_{DS\_kink}),\end{array}$$

(2)

where V_A is Early voltage, C_ox⁽¹⁾ is gate oxide capacitance per square meter, L_o is channel length, μ is the mobility of carriers, and W_eff=19W_o (W_o, fin width), and where β (V^-1) is the kink width adjustment. [16,17,18,19,20,21]

Equation (1) or Equation (2) work as V_DS is less than or larger than (V_GS- V_th), respecitvely. And those parameters, (k_N, V_th, λ, α, β, χ), are deliberately determined to minimize the delta (δ) as follows in Equation (3):

$$\delta =\sqrt{\frac{{\displaystyle \sum _{i=1}^N{(I_{fitting}-I_{measured})}_i^2}}{N}}$$

(3)

2.3. Fitting Algoritm

First, the minimum delta (δ) in Equation (3) may be used to first determine lambda (λ) by adjusting k_N and V_th, leaving the locations of kinks at around V_DS=(V_GS–V_th). Then the discrepancies between the measured data and the fitting data are found to determine (χ, α) in Equation (1) and (2). Finally, the width of the kink (associated with β) at different V_GS is to be determined by, again, the Equation (3). Totally, six parameters are used for the algorithm to well enough fit the characteristic curves. [21]

3. Results

There are three kinds of transistors, namely, FinFET W120L90 (Fin width =120nm, channel length=90nm), MOSFET L180nm (channel length =180nm), and MOSFET L90nm (channel length =90nm). According to the algorithm as described in 2.3, the measured data is fitted with conventional model formula with a little modification like Equation (1) and (2). The determined parameters are listed in Table 1, Table 2, and Table 3 as follows:

As shown in Figure 1 for FinFET, Figure 2 for MOSFET L180, and Figure 3 for MOSFET L090, the fitting without kink (heat or phonon effects) adjustment is presented in (a), where the lambda (λ), k_N, and V_th are found. The differences between the as measured data and the fitting data are thus found in (b). In Figure 1b (double Gate side effects), the mono-peaks are set to where kinks are located and the twin-peaks are set to the shallow valleys in between where kinks are located. In Figure 2b and Figure 3b, there only found are the mono-peaks, where kinks are located. By means of the peaks, the parameters, (χ, α), are thus determined. The beta (β) is varied to find the minimum standard deviation resulting to the (c), (d), and (e). Actually, carriers receive thermal agitations from the kinks, which cause lower current flow.

4. Analysis and Discussion

The three main parameters listed in the Tables are associated with certain physical meanings. It is interesting to see the linearly dependent association as shown in Figure 4 such that kink and (V_GS–V_th) are strongly correlated and linearly dependent to each other as well. This demonstrates and enhances the ideas of the kink effects addressing the phonon disturbances on, scattering from, and coupling with the carriers degrading the electrical performances.

Furthermore, k_N with geometrical fixed sizes is proportional to mobility (μ), which is demonstrated as a constant value at fixed V_GS. But at different applied V_GS bias, mobility is definitely various and proportional to (V_GS-V_th)^-1/3, as shown in Figure 5a, 5b and 5c. In Figure 5b, V_GS=0.8V shall be excluded from the proportionality because less strong inversion layer does not result in effective oxide-silicon interfacial colliding carriers. Moreover, the threshold voltages (V_th) vary at various V_GS not only for FinFET but also for MOSFET, where V_tho may be written as follows:

$$\begin{array}{l}{V}_{tho}=(-0.56-\left|{\Phi }_p\right|{)}_{FB}-\frac{Q_{ox}^{\text{'}}}{C_{ox}^{\text{'}}}+2\left|{\Phi }_p\right|+\frac{Q_{dep}^{\text{'}}}{C_{ox}^{\text{'}}}\\ with\\ \left|{\Phi }_p\right|=\frac{kT}{e}\ln (\frac{p}{n_i}),and\\ Q_{dep}=peD=\sqrt{2{\epsilon }_{Si}pe\left|2{\Phi }_p\right|}\\ where\\ p:\mathit{concentration}\mathit{in}p-\mathit{type}\mathit{semiconductor}\\ and\\ D:\mathit{thickness}\mathit{of}\mathit{depletion}\mathit{region}\end{array}$$

(3)

where “FB” means flat-band voltage, Q_ox is the charge located in the oxide layer, C_ox’ is the unit capacitance, Q_dep is the space charge in the depletion region, and 2|Φ| is the basic applied V_GS that causes the strongly inversed layer for V_tho. Somehow, the Equation (3) is rewritten as the following fitting formula:

$$\begin{array}{l}{V}_{th}=V_{tho}+{\alpha }_{eff}\left|f(V_{GS})\right|+\beta \sqrt{f(V_{GS})}\\ with\\ {\alpha }_{eff}\equiv \mathit{effective}\mathit{screening}\mathit{parameter},\\ \left|\beta \right|=\frac{\sqrt{4{\epsilon }_{Si}pe}}{C{\text{'}}_{OX}},and\\ f(V_{GS})\stackrel{empirically}{\to }=\{\begin{array}{l}1-V_{GS},(FinFET)\\ V_{GS},(MOSFET)\end{array}\end{array}$$

(4)

$\begin{array}{l}where\\ C{\text{'}}_{OX\_FinFET}=(\frac{{\epsilon }_{OX}}{24\times {10}^{-10}})=(\frac{3.9\times 8.85\times {10}^{-12}}{24\times {10}^{-10}}),\\ C{\text{'}}_{OX\_MOSFET}=(\frac{{\epsilon }_{OX}}{60\times {10}^{-10}})=(\frac{5.2\times 8.85\times {10}^{-12}}{60\times {10}^{-10}}),\\ and\\ {\epsilon }_{Si}=11.9{\epsilon }_o=11.9\times 8.85\times {10}^{-12}F/m\end{array}$

In Equation (4), f(V_GS)=(1–V_GS) is defined to deliberately set the condition of V_GS under 1.0 V.[22] In the fitting presented in Figure 6a and 6b, |β|=0.085 and |β|=0.1 correspond to p=4.4×10²³ (1/m³) and p=1.6163×10²² (1/m³), which help identify the thickness of strongly inversed layer to be 182 angstrom at V_{GS_FinFET}=1.0V and 92 angstrom at V_{GS_MOSFET}=0.4V, as referred in Figure 6c.

In addition, λ(|V_A^-1|) signifies the leakage current slope across Source and Drain and shows suppressed as (V_GS–V_th) increases, which means more depletion region induces leakage current reduction, as in Figure 7(a), 7(b), and 7(c).

5. Conclusions

The modified characteristic formulas in Equation (1) and (2) with kink effects (phonon disturbances) provide to fit the as-measured current-voltage curves. The kinks always locate at the joint of Triode region and Saturation region. The standard deviation helps make the fitting as completely as possible such that three parameters (k_N, V_th, λ) are determined. The mobility at certain fixed Gate voltage, which is proportional to k_N, is constant but various at various Gate bias. For FinFET and MOSFET, k_N is found to be almost linearly dependent of (V_GS-V_th)^-1/3, and so is mobility. The determined V_th is found to be V_GS-dependent, too. The empirical equation, which takes advantage of the definition of V_tho, is proposed in order to find β and thus the concentration (p) of doped boron, which may be used to calculate the thickness of the strong inversion layer. In addition, Early Voltage associated λ (|V_A^-1|), which is inversely linearly dependent of (V_GS–V_th), gets flatter as (V_GS–V_th) gets larger. This indicates that higher field more depleting the substrate depresses the leakage current.