Li, Z.; Gao, Z. A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor. Micromachines2024, 15, 578.
Li, Z.; Gao, Z. A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor. Micromachines 2024, 15, 578.
Li, Z.; Gao, Z. A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor. Micromachines2024, 15, 578.
Li, Z.; Gao, Z. A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor. Micromachines 2024, 15, 578.
Abstract
To reduce the redundant counting of TDC in high-speed applications and thus reduce power consumption, a TDC architecture is proposed to quantify the difference between two adjacent rows of pixel signals. This structure can remove the identical part between two rows of pixel signals by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. In the 110nm CMOS process, simulation results show that this design achieves an effective number of bits (ENOB) of 4.72 bits and a Figure of Merit (FoM) of 104.7 fJ/step - 162.3 fJ/step with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.
Keywords
Time-to-digital converters; Image sensors; Low power consumption; High-speed
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
