Yoo, T.; Choi, B.W. Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System. Electronics2024, 13, 733.
Yoo, T.; Choi, B.W. Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System. Electronics 2024, 13, 733.
Yoo, T.; Choi, B.W. Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System. Electronics2024, 13, 733.
Yoo, T.; Choi, B.W. Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System. Electronics 2024, 13, 733.
Abstract
RISC-V offers a modular technical approach combined with an open, royalty-free instruction set architecture (ISA). This openness allows various researches to incorporate RISC-V into both open and proprietary solutions or services. However, despite its advantages as a fundamental building block for many embedded systems, the escalating complexity and functional demands of real-time applications have made adhering to response time deadlines challenging. This has led to an increased demand for comprehensive development insights for real-time systems based on RISC-V. To improve development efficiency, we offer a detailed performance analysis of RISC-V in comparison to various ISAs. In this paper, we analyze the real-time performance of RISC-V through two real-time approaches based on processor architectures. For RTOS applications, we adopted FreeRTOS and evaluated its performance on HiFive1 Rev B (RISC-V) and STM3240G-EVAL (ARM M) to evaluate real-time performance. For Real-time Linux, we utilized Linux with the Preempt-RT patch and tested its performance on VisionFive 2 (RISC-V), MIO5272 (x86-64), and Raspberry Pi 4 B (ARM A). Through these experiments, we examined the real-time mechanism of each operating system. Additionally, in the Preempt-RT experiments, scheduling latencies were evaluated using cyclictest. Finally, in order to practically show the real-time capabilities of RISC-V, we implemented motion control of a six-axis collaborative robot, which was performed on the VisionFive 2 platform. This implementation provided a comparative result of RISC-V’s performance against the x86-64 architecture of MIO-5272. Ultimately, the results indicated that the real-time performance of RISC-V for real-time applications was slightly inferior to that of the x86-64 architecture. A noticeable achievement of this research was the first implementation of an EtherCAT Master on RISC-V designed for real-time applications featuring a multi-tasking structure. The research offers valuable insights into the real-time capabilities of RISC-V compared to established architectures like x86-64. While RISC-V might not surpass these architectures in real-time performance, its flexibility, modularity, and open nature make it a compelling choice for a wide range of real-time applications. The successful implementation of the EtherCAT Master on RISC-V further expands its potential in the domain of real-time embedded control systems.
Keywords
RISC-V; FreeRTOS; PREEMPT-RT; RTOS; EtherCAT; Embedded Linux
Subject
Engineering, Control and Systems Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
