Version 1
: Received: 23 January 2024 / Approved: 24 January 2024 / Online: 24 January 2024 (10:06:33 CET)
How to cite:
Kulisz, J.; Jokiel, F. A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic. Preprints2024, 2024011744. https://doi.org/10.20944/preprints202401.1744.v1
Kulisz, J.; Jokiel, F. A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic. Preprints 2024, 2024011744. https://doi.org/10.20944/preprints202401.1744.v1
Kulisz, J.; Jokiel, F. A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic. Preprints2024, 2024011744. https://doi.org/10.20944/preprints202401.1744.v1
APA Style
Kulisz, J., & Jokiel, F. (2024). A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic. Preprints. https://doi.org/10.20944/preprints202401.1744.v1
Chicago/Turabian Style
Kulisz, J. and Filip Jokiel. 2024 "A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic" Preprints. https://doi.org/10.20944/preprints202401.1744.v1
Abstract
The paper proposes a new implementation of the PID algorithm in digital hardware. The proposed circuit implements an advanced PID formula, containing a non ideal derivative component, and weighting coefficients, which enable reducing influence of setpoint changes in the proportional and derivative components. The implementation operates on standard single precision (32 bit) floating-point numbers. The proposed circuit structure is optimized for cost. It uses just one arithmetic block, performing the multiply-and-add operation. The calculations are carried out in a sequential manner. The circuit was implemented in a Cyclone V FPGA device from Intel, using the Quartus Prime software. Proper operation of the circuit was verified by simulation. The proposed solution is comparable in terms of speed with other hardware implementations of the PID algorithm operating on standard single precision floating-point numbers, while being significantly cheaper. However, it outperforms by several orders of magnitude the speed of any software-based implementation, including solutions using PLCs, and CPU/MCUs. The proposed circuit structure, together with the overall regulator device concept, suit well the SoC (System on Chip), or SoPC (System on Programmable Chip) idea, i. e. a device, that contains a CPU core immersed in “FPGA fabric” - logic resources characteristic for FPGA devices.
Keywords
PID regulator; control systems, FPGA; hardware implementation; floating-point arithmetic
Subject
Computer Science and Mathematics, Hardware and Architecture
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
