Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

Wieslaw Kuzmicz

doi:10.20944/preprints202106.0432.v1

Submitted:

14 June 2021

Posted:

16 June 2021

You are already at the latest version

Subscription

Notify me about updates to this article or when a peer-reviewed version is published.

Preprint

Article

This version is not peer-reviewed.

Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

Wieslaw Kuzmicz^*

A peer-reviewed version of this preprint was published in:

Electronics 2021, 10(15), 1800. https://doi.org/10.3390/electronics10151800

Submitted:

14 June 2021

Posted:

16 June 2021

You are already at the latest version

Abstract

Negative feedback to the back gate of MOS devices available in FD-SOI technologies can be used to improve linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22nm FD-SOI technology illustrate this technique, its advantages and limitations.

Keywords:

CMOS analog integrated circuit

;

FD-SOI

;

feedback

;

linearity

;

operational amplifier

Subject:

Engineering - Electrical and Electronic Engineering

Copyright: This open access article is published under a Creative Commons CC BY 4.0 license, which permit the free download, distribution, and reuse, provided that the author and preprint are cited in any reuse.