Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Version 1 : Received: 1 November 2018 / Approved: 2 November 2018 / Online: 2 November 2018 (10:21:47 CET)

A peer-reviewed article of this Preprint also exists.

Kim, Y.K.; Lee, J.S.; Kim, G.; Park, T.; Kim, H.J.; Cho, Y.P.; Park, Y.J.; Lee, M.J. Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors. Electronics 2019, 8, 8. Kim, Y.K.; Lee, J.S.; Kim, G.; Park, T.; Kim, H.J.; Cho, Y.P.; Park, Y.J.; Lee, M.J. Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors. Electronics 2019, 8, 8.

Abstract

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.

Keywords

gate-induced drain leakage (GIDL), drain-induced barrier lowering (DIBL), recessed channel array transistor (RCAT), on-current (Ion), off-current (Ioff), subthreshold slope (SS), threshold voltage (VTH), saddle FinFET (S-FinFET), Potential Drop Width (PDW), Shallow Trench Isolation (STI).

Subject

Engineering, Electrical and Electronic Engineering

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