Preprint Article Version 1 This version is not peer-reviewed

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors

Version 1 : Received: 16 June 2018 / Approved: 18 June 2018 / Online: 18 June 2018 (15:48:37 CEST)
Version 2 : Received: 4 September 2018 / Approved: 5 September 2018 / Online: 5 September 2018 (05:45:16 CEST)

A peer-reviewed article of this Preprint also exists.

Gu, Y.; Yan, D.; Verma, V.; Wang, P.; Stan, M.R.; Zhang, X. Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors. J. Low Power Electron. Appl. 2018, 8, 28. Gu, Y.; Yan, D.; Verma, V.; Wang, P.; Stan, M.R.; Zhang, X. Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors. J. Low Power Electron. Appl. 2018, 8, 28.

Journal reference: J. Low Power Electron. Appl. 2018, 8, 28
DOI: 10.3390/jlpea8030028

Abstract

Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property in near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up.

Subject Areas

Near Threshold Computing (NTC); Dual-Supply; Static Random Access Memory (SRAM); Reliability; Write Aggregation Buffer

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