Version 1
: Received: 3 April 2018 / Approved: 10 April 2018 / Online: 10 April 2018 (15:41:39 CEST)
How to cite:
Dong, E.; Yuan, M.; Tong, J.; Du, S.; Chen, Z. Topological Horseshoe Analysis and FPGA Implementation of the Fractional-order Liu System. Preprints2018, 2018040129. https://doi.org/10.20944/preprints201804.0129.v1
Dong, E.; Yuan, M.; Tong, J.; Du, S.; Chen, Z. Topological Horseshoe Analysis and FPGA Implementation of the Fractional-order Liu System. Preprints 2018, 2018040129. https://doi.org/10.20944/preprints201804.0129.v1
Dong, E.; Yuan, M.; Tong, J.; Du, S.; Chen, Z. Topological Horseshoe Analysis and FPGA Implementation of the Fractional-order Liu System. Preprints2018, 2018040129. https://doi.org/10.20944/preprints201804.0129.v1
APA Style
Dong, E., Yuan, M., Tong, J., Du, S., & Chen, Z. (2018). Topological Horseshoe Analysis and FPGA Implementation of the Fractional-order Liu System. Preprints. https://doi.org/10.20944/preprints201804.0129.v1
Chicago/Turabian Style
Dong, E., Shengzhi Du and Zengqiang Chen. 2018 "Topological Horseshoe Analysis and FPGA Implementation of the Fractional-order Liu System" Preprints. https://doi.org/10.20944/preprints201804.0129.v1
Abstract
This paper first discusses a fractional-order Liu system of order as low as 2.7 and shows its chaotic characteristics by carrying out numerical simulations such as Lyapunov exponents, bifurcation diagrams and phase portraits. Then, by using the topological horseshoe theory and computer-assisted proof, the existence of chaos in the system is verified theoretically. Finally, the fractional-order system is implemented on a Field Programmable Gate Array (FPGA) and the results obtained show that the fractional-order Liu system is indeed chaotic.
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
