The advantage of FPGAs lies in the ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small "soft-core" processor implementing I/O in software. With the goal to design and evaluate a new tiny soft-core processor optimized for FPGA resources in I/O , a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources including program size for 8-bit applications. The number of instructions is not large but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.

In this paper, a novel integrated high precision vacuum microelectronic accelerometer is put forward based on the theory of field emission, the accelerometer consists of sensitive structure and interface ASIC. The sensitive structure has a mass of a cathode cone tips array, a folded beam, an emitter electrode and a feedback electrode. The sensor is fabricated on a double side polished (1 0 0) N-type silicon wafer, the tips array of cathode are shaped by wet etching with HNA (HNO3, HF and CH3COOH) and metalized by TiW/Au thin film. The structure of sensor is released by ICP process finally. The interface ASIC was designed and fabricated based on the P-JFET high voltage bipolar process. The accelerometer is tested through static field rollover test, and the test results show the integrated vacuum microelectronic accelerometer has good performances, which sensitivity is 3.081V/g and non-linearity is 0.84% in the measuring range of −1g~1g.

This paper provides a comparative analysis of AES (Advanced Encryption Standard) and Salsa20 algorithm implementations, focusing on power consumption efficiency in passive RFID (Radio Frequency Identification) tags and ultra-low-power devices. The main objective of this work is to determine which of these algorithms is more suitable to operate in these types of devices. For this purpose, ASIC (Application-Specific Integrated Circuit) implementations of AES and Salsa20 based on low-power approaches were developed and their power consumption was evaluated. Results demonstrate that Salsa20 power consumption is lower than AES (2.82μW and 4.01μW, respectively - both in 0.18μm), indicating that Salsa20 is a better choice than AES for passive RFID tags.