Significance-Weighted Tolerance Allocation for Binary-Weighted Measurement Systems Built from Discrete Components: A Closed-Form Rule and Its Validity Boundary

1. Introduction

Many measurement systems resolve an unknown quantity by comparing it with a set of physical references whose values follow powers of two. The successive-approximation-register (SAR) analogue-to-digital converter is the best-known example [1,2], but the same structure appears in binary-weighted resistor networks, in weighing with a set of binary reference masses, and in threshold banks that convert a physical quantity into a binary code through a binary search. In each case the accuracy of the result depends on how closely the realised references follow their nominal binary ratios.

When such a system is assembled from discrete parts, each reference element is purchased or manufactured to a tolerance class, and the usual engineering practice is to specify one class for all elements. The contribution of an element to the output error, however, scales with its weight: an error of 0.1 % in the most significant element of a 10-bit system displaces the result by about half a least significant bit (LSB), whereas the same relative error in the least significant element displaces it by one thousandth of an LSB. A uniform specification therefore buys precision where it has almost no effect.

Allocating tolerances to minimise cost for a required functional accuracy is an established problem in mechanical design, where the cost of each dimension is modelled as a decreasing function of its tolerance and the assembly tolerance is a combination of the component tolerances [3,4,5,6]. The reciprocal-square cost model proposed by Spotts [3], for example, leads to allocations in which each tolerance is weighted by its sensitivity. In integrated circuits, the analogous trade-off between matching accuracy and device area follows from the Pelgrom mismatch law [7,8]. Post-fabrication calibration, which estimates and corrects the realised weights of each unit, is the other established remedy [9,10]; it acts after assembly, whereas allocation acts on the specification. Methods for discrete tolerance classes, where the cost–tolerance relation is a step function, have also been developed, for example the slope-based method of Nagarwala et al [6]. To the author's knowledge, the tolerance-allocation view has not been applied explicitly to binary-weighted measurement systems built from discrete references, in which the sensitivity of each element is fixed by its binary weight.

The hypothesis examined in this paper, proposed by the author, is that the precision of each reference element in a binary-weighted measurement system should follow its significance rather than being uniform, and that doing so reduces component cost substantially at unchanged measurement quality. The contributions are as follows.

(i) A closed-form, error-variance-optimal tolerance allocation t_i ∝ W_i^−2/(α+2) for a power-law cost model, together with an explicit expression for the achievable cost ratio and its asymptotic 1/N behaviour (Section 3).

(ii) A yield-constrained allocation over catalogue tolerance classes, evaluated by Monte Carlo static testing and validated on independent units, showing that the variance-optimal rule and the yield-optimal selection differ and why (Section 4 and Section 5).

(iii) A validity boundary for integrated capacitor arrays. SPICE Monte Carlo shows that unit-cell arrays already satisfy the α = 2 optimum under area-only mismatch (Section 5.5), and a layout-level study shows that coarser cells for the significant bits help at equal area only when edge mismatch is significant and gradients are moderate (Section 5.6).

2. System model

2.1. Binary-weighted conversion with toleranced references

An N-bit binary-weighted system is considered with index i = 1 for the least significant bit (LSB) and i = N for the most significant bit (MSB). The nominal weights, in units of the LSB q, are

W_i = 2ⁱ⁻¹ q, i = 1, …, N. (1)

Each weight is realised by one physical element whose relative deviation δ_i is bounded by the tolerance class t_i of that element:

Ŵ_i = W_i(1 + Δ_i), |Δ_i| ≤ t_i. (2)

As a conservative model, δ_i is taken as uniformly distributed on [−t_i, t_i]; a truncated Gaussian with standard deviation t_i/3 is used as a robustness case. The conversion is a binary search: starting from the MSB, the element is retained if the residue exceeds the realised weight plus comparator noise, and removed otherwise. The digital output is reconstructed with the nominal weights, as in a system whose firmware knows only the nominal part values. Comparator noise of 0.25 LSB rms and input noise of 0.01 LSB rms are included.

2.2. Error variance

For a uniformly distributed input, each decision b_i equals 1 with probability 1/2, so E[b_i²] = 1/2. To first order, the error caused by the reference deviations is the weighted sum of the deviations of the retained elements, and its variance is

${\sigma }^2={\displaystyle \frac{1}{2}}{\displaystyle {\sum }_{i=1}^N}{W_i}^2\mathit{var}\left({\Delta }_i\right)={\displaystyle \frac{1}{6}}{\displaystyle {\sum }_{i=1}^N}{W_i}^2{t_i}^2,$     (3)

where the second equality uses var(δ_i) = t_i²/3 for the uniform model. The factor W_i² expresses the unequal significance of the elements: the MSB of a 10-bit system carries 2¹⁸ ≈ 2.6 × 10⁵ times the variance weight of the LSB. Equation (3) treats the decisions as independent of the deviations. This is a first-order approximation, since the decisions depend on the residue and therefore on the realised weights. The deviations considered here (at most 1 % of each weight) move each decision threshold by a small fraction of that weight, however, so the dependence enters only at second order. Section 5.1 tests the approximation directly against the full Monte Carlo model, which contains all of these effects.

2.3. Cost model

The cost of a toleranced element is modelled by the reciprocal power law

$C=\kappa {\displaystyle {\sum }_{i=1}^N}{t_i}^{-\alpha },$     (4)

where κ is a price scale and α > 0 describes how steeply price rises as tolerance tightens. The special case α = 2 is the reciprocal-square model of mechanical tolerancing [3] and is also the matching-area model of integrated devices, since the Pelgrom law gives σ ∝ A^−1/2 and hence area ∝ σ⁻² [7]. To anchor α, the unit prices of 120 surface-mount resistors (case 0805, 10 kΩ) in the seven tolerance classes of Section 4 were taken from a distributor catalogue [11] (Table 4). A least-squares fit of log price against log(1/t) gives α = 1.16 for the class median (R² = 0.95, bootstrap 95 % interval 0.88–1.34) and α = 1.30 for the cheapest part in each class (R² = 0.91, 1.02–1.50). The case α = 1 is therefore representative of discrete resistors. Because prices within one class vary by more than an order of magnitude between series, results are reported for 0.5 ≤ α ≤ 3, and Section 5.2 also repeats the selection with the catalogue prices themselves.

3. Closed-Form Allocation

3.1. Optimal Tolerances

Minimising the cost (4) subject to a prescribed error variance (3) is a convex problem in the variables t_i > 0. With the Lagrangian L = κΣt_i^−α + μ(ΣW_i²t_i² − 6σ²), the stationarity condition −ακt_i^−α−1 + 2μW_i²t_i = 0 gives t_i^α+2 ∝ W_i⁻², that is

$t_i^{*}=\lambda {W_i}^{-2/(\alpha +2)},$     (5)

with λ fixed by the variance constraint. For binary weights, the optimal tolerance tightens by the constant factor 2^2/(α+2) from one bit to the next: a factor of 1.59 for α = 1 and √2 for α = 2. The rule has a direct interpretation. At the optimum the marginal cost of reducing the variance is the same for every element, so no reallocation of spending between elements can reduce the cost further.

3.2. Achievable Cost Ratio

A uniform design with the same variance uses t_u² = 6σ²/ΣW_i². Substituting (5) and the uniform design into (4) gives the ratio of the optimal to the uniform cost at equal error variance,

$R(\alpha ,N)={\displaystyle \frac{{\left({\displaystyle {\sum }_{i=1}^N}{W_i}^p\right)}^{1+\alpha /2}}{N{\left({\displaystyle {\sum }_{i=1}^N}{W_i}^2\right)}^{\alpha /2}}},p={\displaystyle \frac{2\alpha }{\alpha +2}}.$     (6)

For α = 2, (6) reduces to R = (ΣW_i)²/(NΣW_i²), which is at most 1 by the Cauchy–Schwarz inequality, with equality only if all weights are equal. For binary weights and large N, ΣW_i ≈ 2^N and ΣW_i² ≈ 4^N/3, so R ≈ 3/N. More generally, R(α, N) ≈ 3^α/2/[N(2^p − 1)^1+α/2]: the saving of the significance-weighted design grows with resolution. Figure 1 shows the saving 1 − R for 6 ≤ N ≤ 16. For N = 10 the saving is 49.5 %, 62.1 % and 70.1 % for α = 0.5, 1 and 2.

4. Simulation Methodology

All results in Section 5.1 to 5.4 were obtained with a behavioural Monte Carlo model of the converter of Section 2. Each simulated unit draws one set of deviations δ_i, which is fixed for that unit. Two figures of merit are computed per unit.

(a) Static linearity. Differential and integral nonlinearity (DNL, INL) are obtained by a code-density test with 32 samples per code. Comparator and input noise are switched off in this test, so the yield reflects the reference deviations alone, and INL is referred to the endpoint line [12]. A unit passes if both |INL| and |DNL| are at most 0.5 LSB. The yield is the fraction of passing units; its 95 % confidence interval is given by the Wilson score interval.

(b) Conversion RMSE. The root-mean-square difference between the reconstructed output and the input is computed over 4000 uniformly distributed inputs with comparator and input noise included. With ideal references the RMSE is 0.382 LSB, set by quantisation (1/√12 = 0.289 LSB) and comparator noise (0.25 LSB) added in quadrature. Differences in RMSE between designs are therefore differences in the reference contribution above this floor.

The available tolerance classes are 1 %, 0.5 %, 0.25 %, 0.1 %, 0.05 %, 0.02 % and 0.01 %. For the yield-constrained designs, classes are selected by a greedy procedure. Starting from 1 % for every element, it repeatedly tightens the one element that gives the largest yield increase per unit of added cost. It stops when the yield on a training set of 500 units reaches 99.5 %. The selection is constrained so that a more significant element is never assigned a looser class than a less significant one. Every selected design, and every uniform reference design, is then re-evaluated on an independent validation set of 3000 units generated with a different random seed. All reported yields, RMSE values and costs come from that validation set. The margin between the 99.5 % training target and the 99 % acceptance level absorbs the sampling error of the training set.

The simulation code (Python, ngspice and MATLAB) was written with the assistance of a generative AI tool (Claude, Anthropic), as stated in the Acknowledgements. The author defined the models and acceptance criteria and checked the code and its outputs; the code is openly available (see the Data availability statement).

5. Results

5.1. Verification of the closed form

The continuous allocation (5) was evaluated for N = 10 against a uniform tolerance of 0.1 %, scaled so that both designs have the same error variance (3). The results over 2000 units are given in Table 1. The RMSE of the two designs agrees to within 0.5 % (0.452 and 0.450 LSB for α = 1), and the Monte Carlo cost ratios, 0.379 for α = 1 and 0.299 for α = 2, coincide with (6). The closed form is therefore confirmed for the quantity it optimises, including the first-order independence assumption behind (3). The uniform 0.1 % yield here (85.4 %, 2000 units) differs slightly from that in Table 2 (87.1 %, 3000 units) because the two are independent random samples; their 95 % confidence intervals overlap.

The same table shows that the variance-optimal design has a lower linearity yield than the uniform design (77.5 % against 85.4 % for α = 1). The reason is the endpoint reference line used for INL. It removes the gain error of each unit, and for a uniform relative tolerance the gain error is dominated by the MSB, the same element that dominates the nonlinearity. Much of the MSB's deviation therefore disappears into the gain correction. When the LSB-side elements are loosened, their deviations are no longer proportional to those of the MSB and are not removed by the gain correction. Variance-optimal and yield-optimal allocations therefore differ. A variance criterion suits applications that report absolute error without gain calibration, whereas a linearity-yield criterion suits systems in which a one-point gain calibration is routine. The latter is treated next.

5.2. Yield-Constrained Selection from Tolerance Classes

Table 2 lists the uniform reference designs for N = 10. A single class of 0.1 % yields only 87.1 % of units within ±0.5 LSB, so a uniform design requires 0.05 % throughout to exceed 99 % yield. Table 3 gives the designs selected for α = 0.5, 1 and 2 and their validation results.

At α = 1 the selected design keeps the three least significant elements at 1 %, and only the two most significant elements need the 0.05 % class used everywhere in the uniform design. The validated yield is 99.8 % (95 % CI 99.5–99.9 %) and the RMSE is 0.405 LSB, against 0.400 LSB for the uniform 0.05 % design. The saving is 63.5 %. The savings for α = 0.5 and 2 are 48.0 % and 73.8 %. They are smaller than the variance-optimal values of Figure 1 because the classes are discrete and because of the yield criterion discussed in Section 5.1. They are nevertheless large for every cost exponent considered. To measure how far the greedy selection is from the true optimum, all 8008 ordered class vectors for N = 10 were searched exhaustively in order of increasing cost under the same training criterion. For α = 0.5 and α = 1 the greedy designs are the exact optima. For α = 2 the optimum loosens the three least significant elements from 0.5 % to 1 % and costs 1039 instead of 1048 units (0.9 % less), which raises the saving from 73.8 % to 74.0 %. The greedy procedure is therefore at or within 1 % of the optimum. Figure 2 compares the selected classes with the continuous rule (5), and Figure 3 places the selected design on the yield–cost plane of the uniform designs. Finally, the exhaustive search was repeated with the catalogue prices of Table 4 in place of the power law. Market prices are step-like and not even monotonic (the cheapest 0.01 % part costs less than the cheapest 0.02 % part), so this is a direct test of the conclusions against real costs. With median prices the optimum is the design of Table 3 for α = 1, at 310.7 INR against 853.7 INR for uniform 0.05 %, a saving of 63.6 %. With the cheapest part in each class the optimum (1 / 1 / 1 / 0.5 / 0.5 / 0.1 / 0.1 / 0.1 / 0.05 / 0.05 %) saves 66.6 % (102.3 against 306.7 INR). Validated yields are 99.8 % and 99.8 %.

5.3. Robustness to the Tolerance Distribution

Manufactured parts are often distributed more narrowly than their tolerance bound. The design selected for α = 1 under the uniform model was therefore re-validated with deviations drawn from a truncated Gaussian of standard deviation t_i/3, without re-selection. The yield was 100.0 % (95 % CI 99.9–100.0 %). Under the same model the uniform 0.1 % design reaches 98.9 % and still falls short of 99 %, so the cheapest passing uniform design remains 0.05 % and the saving is unchanged at 63.5 %. Selection under the uniform model is thus conservative with respect to more concentrated distributions.

5.4. Resolution

Table 5 repeats the selection for other resolutions at α = 1. In agreement with the 1/N trend of Section 3.2, the saving grows with resolution, from 40.6 % at 8 bits to 63.5 % at 10 bits and 76.5 % at 12 bits, because the spread of significance between the most and least significant elements grows as 2^N−1. At 12 bits the uniform design needs the tightest class considered (0.01 %) for every element, and the uniform 0.02 % design reaches only 95.7 % yield. The allocated design uses that class only for the MSB and keeps the four least significant elements at 0.5 %. At higher resolution the tightest available class, rather than cost, becomes the limit for a uniform design, whereas an allocated design needs it for only one or two elements.

5.5. Validity Boundary: Integrated Unit-Cell Arrays

The rule assumes that each element can be assigned its own tolerance independently of its nominal value. This holds for discrete parts but not for an integrated capacitor array built from unit cells. To test the boundary, a 10-bit charge-redistribution array was simulated in ngspice [13] using the metal–insulator–metal capacitor model of the open SkyWater SKY130 process design kit [14]. That model specifies a mismatch of σ_C/C = 2.8 %/√(WL/µm²). Each bit was built from 2ⁱ⁻¹ unit cells of 4 µm × 4 µm, and 300 Monte Carlo instances were run. The relative standard deviation of each bit capacitance follows the Pelgrom scaling, from 0.73 % for the LSB to 0.0314 % for the MSB, against 0.0321 % predicted from the LSB value by W^−1/2 (Figure 4).

This scaling is exactly the optimum (5) for α = 2, which is the matching-area cost of integrated devices. A unit-cell array therefore already realises the significance-weighted allocation, with no design effort. Uniform enlargement of the whole array by a factor of 8 in area changed the conversion RMSE by less than 3 % (0.393 and 0.383 LSB), confirming that mismatch was not limiting. Conversely, enlarging only the cells of the three MSBs (3 × 3 area) destroys the binary ratios themselves, because in a capacitor array the weight is the capacitance: DNL rose to about 126 LSB and the SNDR fell from 59.2 dB to 19.8 dB. Nonuniform precision in an integrated array can only be obtained by means that keep the capacitance ratios, such as building each bit from cells of a different size, which introduces systematic ratio errors of its own. Under area-only mismatch the allocation rule therefore gives no gain for integrated unit-cell arrays; Section 5.6 examines when this changes. For systems whose elements are specified individually, the uniform-class practice is far from optimal.

5.6. Integrated Capacitor Arrays: Edge Mismatch, Gradients and the Limit of the Rule

Area-only mismatch. In an integrated capacitive DAC the cost of precision is area. If the relative mismatch of a capacitor of area A_i follows the area law σ²(ΔC_i/C_i) = K²/A_i [7], the error variance Σ C_i²K²/A_i is minimised under a fixed total area Σ A_i = A_tot by

A_i ∝ C_i, (7)

which follows from the Cauchy–Schwarz inequality and is exactly the conventional array of identical unit cells. Under this model no reallocation of area between bits can improve accuracy at equal area; this is the α = 2 case of the allocation rule, in agreement with Section 5.5. The mismatch model of the SKY130 metal–insulator–metal capacitor is of this form, σ(ΔC)/C = 2.8 %/√(WL) with W and L in µm [14], and measurements on small metal fringe capacitors are also consistent with area scaling [15].

Edge mismatch. The conclusion rests on the area law alone. Random edge roughness adds a variance proportional to the perimeter [16]. For a square cell of s unit capacitances,

$\mathit{var}(\Delta C_{\mathit{cell}})={\sigma }_u^2\left[\right(1-\rho )s+\rho \sqrt{s}],$     (8)

where σ_u is the relative standard deviation of one unit cell and ρ is the share of its variance that comes from the edge. A bit of weight W_i built from W_i/s_i cells of size s_i then has

$\mathit{var}(\Delta C_i)={\sigma }_u^2{W}_i\left[\right(1-\rho )+\rho s_i^{-1/2}],$     (9)

so building a bit from fewer, larger cells reduces its edge contribution at unchanged capacitance. Three effects oppose this: a larger cell has a smaller fringe share and needs slightly more area for the same capacitance; cells of different size carry a systematic ratio error when the fringe coefficient deviates from its nominal value; and fewer, larger cells are harder to place in a common centroid, which exposes them to process gradients. The design family studied here uses cells of size s_i = min(W_i, S), so the significant bits are built from cells of S units and the bits smaller than S are single cells; S = 1 is the conventional array.

Method. A 10-bit array of 2¹⁰ unit sites was simulated in MATLAB with σ_u = 0.8 %, which gives the conventional array a linearity yield of about 94 %. The systematic fringe error of a cell of size s was fηz(s^−1/2 − 1), with fringe fraction f = 0.05, uncertainty η of the fringe coefficient and z ~ N(0, 1) per die. The area overhead of larger cells was computed from the same fringe model (at most 4.9 % for S = 512), and each design was then shrunk to the area of the conventional array, which multiplies the area term of (8) by the area ratio r and the edge term by r^3/2. For every S an explicit layout was generated: bits with at least two cells receive point-symmetric pairs of cells from the centre outwards, so that a linear gradient cancels exactly, and the bits smaller than S share one central block split in binary halves. The capacitance density was 1 + g_xu + g_yv + q_xxu² + q_yyv² + q_xyuv over the normalised array coordinates u and v, with g_x, g_y ~ N(0, g_s) and q_xx, q_yy, q_xy ~ N(0, g_s/2) per die, where g_s is the relative density change at the array edge. Yield was defined as max|DNL| ≤ 0.5 LSB and max|INL| ≤ 0.5 LSB (endpoint fit, all codes). For each parameter set the best S was selected on 10 000 training dies and compared with the conventional array on 40 000 independent test dies drawn with the same random numbers for both designs (paired comparison, 95 % Wilson intervals).

Results. Table 6 isolates the edge effect without gradients (η = 0.10). With ρ = 0 the procedure selects the conventional array, as (7) requires. With ρ > 0 the coarse-cell designs are better at equal area, and the gain grows with ρ.

Table 7 adds gradients and common-centroid placement. Gradients penalise large cells and move the optimum towards smaller S; whenever a gradient was present and a gain remained, the selected cell size was S = 8. For ρ = 0.25 the rms INL falls by 8.2 %, 6.3 % and 2.9 % for g_s = 0, 0.001 and 0.003; for ρ = 0.5 it falls by 21.2 %, 15.5 % and 11.7 %. For ρ = 0.10 the gain is at most 0.4 percentage points of yield, and for g_s = 0.01 the conventional array is selected at every ρ. In no case did the selected design perform worse than the conventional array on the test set.

Scope. These results define where a nonuniform allocation can improve an integrated array at equal area; they do not show that a particular process lies in that region. No published, verifiable fit of the edge share ρ or of the gradient magnitude g_s was found for the capacitor types used in SAR DACs, and the SKY130 model [14] corresponds to ρ = 0, for which no gain exists. For integrated arrays the rule is therefore conditional: it applies to processes or capacitor structures with a significant edge component and moderate gradients, and ρ must be determined for each process. A simple test structure suffices: single cells of 1, 4, 16 and 64 unit capacitances, whose measured variances, plotted against (8), separate the area and edge terms. Routing and top-plate parasitics, the dependence of the fringe fraction on cell size after shrinking, and comparator noise were not modelled. For arrays assembled from individually specified discrete parts none of these restrictions applies, which is why the main results of this paper concern such systems.

6. Discussion

Scope of application. The results apply to any binary-weighted measurement system whose references are individually specified parts: resistor-array converters and sensor interfaces, sets of binary reference masses, banks of binary optical or radiation attenuators, and hydraulic or mechanical threshold banks resolved by binary search. In all of these, the designer chooses one tolerance per element and pays per element. Equation (5) then gives the direction and the rate of tightening, and the yield-constrained selection gives a purchasable design.

Practical significance. For low-cost chip resistors the absolute saving per unit is small. For the 12-bit design with the catalogue prices of Table 4, the resistor set costs 406 INR instead of 1145 INR with the cheapest parts, and 1722 INR instead of 5515 INR with median parts (about US$4.2 against US$11.9, and US$18 against US$57, at 95.95 INR per US$ on 30 September 2026). This figure uses the 12-bit selection of Table 5 with one market correction: because 0.02 % parts cost more than 0.01 % parts in Table 4, the two 0.02 % elements are replaced by 0.01 % parts, which is both cheaper and tighter. The corrected design was re-validated on 3000 units, with a yield of 100.0 % (95 % CI 99.9–100.0 %). The saving matters in three situations. First, in series production it scales with volume and requires only a different bill of materials, with no change to the circuit or the firmware. Second, where each reference element is itself expensive, such as bulk-metal-foil resistors, calibrated reference weights of a high accuracy class, or radiation and optical attenuators, the same percentage corresponds to a large absolute amount. Third, and most important at high resolution, the constraint becomes availability rather than price. At 12 bits a uniform design already needs the tightest catalogue class for every element, whereas the allocated design needs it for three. Beyond this resolution a uniform design would need a class tighter than any in Table 4, while an allocated design can still be built from available parts for its less significant elements.

Choice of criterion. Section 5.1 shows that the allocation depends on how quality is judged. If absolute error without gain calibration matters, the variance rule (5) is optimal. If linearity after a gain correction is the acceptance criterion, as is common in instrumentation, the selection should be made on yield. In both cases the least significant elements can be relaxed by one or more tolerance classes. A practical procedure is to compute (5) for the parts considered, round each tolerance to the nearest catalogue class, and then check or refine the design by yield simulation as in Section 5.2.

Relation to calibration. Allocation acts on the distribution of the deviations before assembly, whereas calibration measures and corrects the deviations of a finished unit. A system whose MSB elements are tight needs a smaller correction range, and one whose LSB elements are loose adds deviations of below 0.1 LSB. The two measures are therefore complementary.

Limitations. (1) The power law fits catalogue prices only approximately, and prices depend on series and supplier; the direct search with catalogue prices (Section 5.2) gives savings consistent with the fitted α, but a designer should repeat it with the parts actually considered. (2) Temperature coefficient and long-term drift, which also scale with tolerance class in practice, are not modelled. (3) Nominal-value quantisation of standard resistor series is assumed to be known to the firmware and is not treated as error. (4) The greedy selection is not guaranteed to be optimal in general; for N = 10 it was checked against exhaustive search (Section 5.2). (5) The simulations are behavioural. Experimental confirmation with purchased parts is the natural next step.

7. Conclusion

The author's hypothesis that reference precision in a binary-weighted measurement system should follow significance was formulated as a tolerance-allocation problem and confirmed. For a power-law cost, the variance-optimal tolerances follow t_i ∝ W_i^−2/(α+2), with a closed-form cost ratio that falls as about 1/N. Under a linearity-yield criterion with catalogue classes and independent validation, a 10-bit design at ≥99 % yield costs 48.0–73.8 % less than the cheapest uniform design, and the saving increases with resolution. The same analysis shows that integrated unit-cell arrays already sit at the α = 2 optimum under area-only mismatch; there, coarser cells for the significant bits give a gain at equal area only when edge mismatch is significant and gradients are moderate. The rule applies directly to systems built from individually specified references, which are common in measurement practice.