A PVT-Compensated All-Digital Multi-Modulus Divider in 22 nm FDSOI Using Back-Gate Corner Closure

The first divider in an integer- or fractional-N frequency synthesizer runs at the full oscillator frequency and so constrains both the speed and the power of the loop. Current-mode logic (CML) reaches high speed but draws a constant bias current independent of activity, whereas a fully static-CMOS (all-digital) divider draws only dynamic and leakage current at the cost of much greater timing sensitivity to process, voltage, and temperature (PVT) variation. This paper presents a wide-range all-digital multi-modulus divider in a 22 nm fully depleted silicon-on-insulator (FDSOI) technology, characterized entirely by post-layout and Monte Carlo simulation, together with the methodology that makes the timing-sensitive digital approach robust. The all-digital chain exhibits three PVT failure modes, setup at the slow-hot corner, hold at the fast-cold corner, and internal duty-cycle collapse at the skewed corners; each is predicted analytically and closed by a three-method scheme built on the FDSOI back gate, a per-stage delay trim, and a systematic integral-nonlinearity trim. The divider covers N=8 to 127 at up to 39.5 GHz at the typical corner, with every process corner held at or above 35 GHz by back-gate compensation, the highest speed among the compared dividers and the only one with explicit PVT compensation. At the 33 GHz target it consumes 5.3 mW at N=127 (6.2 GHz/mW) with an activity-scaling supply current, benchmarked against the measured power of published CML dividers. Per-die body-bias and trim raise the Monte Carlo yield from 78% to 99.3%, at 150 fs additive jitter, in a compact 0.005 mm² core.