Design and Numerical Demonstration of All-Optical Logic Devices Based on Topological Valley Photonic Crystals with Circular Ring Dielectric Columns

1. Introduction

With the rapid development of artificial intelligence and big data, traditional electronic computing is approaching its physical limits—the slowdown of Moore's Law and the increasing severity of power consumption issues. By harnessing the inherent ultra-high speed and parallel processing capability of photons, all-optical information processing serves as a core enabling technology for breaking through this bottleneck [1,2,3,4]. To realize all-optical computing, the key lies in developing on-chip all-optical logic devices that combine compact, low-loss, and highly robust [5,6,7,8,9,10]. However, conventional approaches based on nonlinear effects or microring resonators often face limitations such as large device footprints, high power consumption, limited bandwidth, and sensitivity to fabrication errors—factors that severely hinder their integration. For instance, interferometric logic gates, while structurally simple, are highly sensitive to the output phase and suffer from considerable power attenuation, which makes cascading difficult.

The rise of topological photonics offers a new approach to addressing these challenges [11,12]. Its core is to use the topological invariants of materials to construct topologically protected photonic edge states [13]. These edge states are inherently robust against structural defects, disorder perturbations, and sharp bends, thus enabling low-loss and backscattering-immune optical transmission [14,15]. In particular, VPCs, which serve as a typical two-dimensional topological photonic platform [16,17,18,19,20], generate non-zero valley Chern numbers at the valleys of the Brillouin zone by breaking spatial inversion symmetry, thereby inducing valley-selective unidirectional edge states and laying a theoretical foundation for developing compact and robust photonic devices. In recent years, VPC-based devices such as power splitters, wavelength-division multiplexers, and optical switches have been extensively explored, demonstrating the performance advantages conferred by topological protection [21,22,23,24,25,26,27,28].

However, conventional VPCs based on solid dielectric columns offer limited design freedom, which restricts the flexible control of band structures and edge states. Integrating multiple logic functions on a single compact platform also remains an open challenge [29,30,31].

Inspired by recent studies [32,33] and to address the above challenges, we propose a topological VPC based on circular ring dielectric columns. By introducing the inner radius as an independent tuning parameter, we expand the control over the band structure beyond the conventional outer radius and lattice constant. This enables complete spectral separation of two types of topological edge states (TES), fundamentally eliminating multi-channel crosstalk. Using this platform, we demonstrate a 50:50 beam splitter (BS) with an insertion loss below 0.5 dB across the operational band and as low as 0.21 dB at 193.5 THz. Leveraging reciprocity and interference effects, we realize OR, XOR, and NOT logic gates on the same structure, and further demonstrate an AND gate through cascading. All devices exhibit an extinction ratio of 18.9 dB at 1550 nm, with the XOR gate reaching up to 44 dB, and maintain stable performance over a broad frequency range.

2. Materials and Methods

In this work, we construct VPCs based on circular ring dielectric columns. Figure 1 illustrates the structural characteristics and band properties of the VPCs. Figure 1a shows a schematic of the periodic lattice and the unit cell. The photonic crystal consists of circular ring dielectric columns arranged in a triangular lattice with lattice constant $a=430nm$. The lattice basis vectors are ${\mathit{a}}_1=a/2i+a\sqrt{3}/2j,{\mathit{a}}_2=ai$. The parallelogram in the figure marks a unit cell of the VPC. The background is air, and the dark regions represent silicon ring columns with refractive index n=3.48 and relative permeability ${\mu }_r$=1. Two types of ring columns, A and B, are defined with the following geometric parameters: for column A, outer radius $R_{11}=0.25a$ and inner radius $R_{12}=0.25R_{11}$; for column B, outer radius $R_{21}=0.19a$ and inner radius $R_{22}=0.5R_{21}$. Based on these parameters, we obtain two distinct unit cells, labeled VPC1 and VPC2. Using finite-element method simulations, we calculate the band structures of the VPCs. Figure 1b presents the band structure along the high-symmetry path in the Brillouin zone, where the blue region indicates the topological photonic band gap. The eigenstate distribution at the K point for VPC1 is also shown. Calculations confirm that VPC1 and VPC2 possess valley Chern numbers of opposite signs at the K and K′ points, indicating distinct and complementary topological phases [33]. Throughout this work, only the transverse-magnetic (TM) mode is considered.

To construct topologically protected edge states, we combine VPC1 and VPC2 with opposite topological phases to form a sandwich-like supercell, as shown in Figure 2a,. At interfaces I and II, this structure supports TES1 and TES2, respectively. As shown in Figure 2b, the band structure of the initial configuration reveals that TES1 operates within the frequency range of 172.5–187.5 THz, with TES2 covering 182.75–198.75 THz. The dispersion curves consist of two pairs of separated linear branches with opposite slopes. For comparison, a previous study reported a relative band gap width of $∆\omega /{\omega }_c=12.7\mathrm{\%}$ (where ${\omega }_c$is the mid-gap frequency) in Ref. [34]. In this work, the overall relative band gap width is $∆\omega /{\omega }_c=14.3\mathrm{\%}$, with TES1 and TES2 exhibiting relative bandwidths of 8.33% and 8.39%, respectively. Notably, the two bands exhibit significant overlap, which can induce inter-valley scattering, causing crosstalk and reducing the effective operational bandwidth [35]. Figure 2c shows the electric field distribution and Poynting vector at k=0.4, confirming the topological locking between propagation direction and valley degree of freedom [36].

To achieve high-performance logic devices with broader operational bandwidth and enhanced crosstalk immunity, we introduce a radius ratio parameter γ, defined as the ratio of inner radius to outer radius. Specifically, ${\gamma }_A=R_{12}$/$R_{11}$ and ${\gamma }_B$=$R_{22}$/$R_{21}$. Fixing the outer radii at $R_{11}=0.25a$ and $R_{21}=0.19a$, we systematically scan ${\gamma }_A$ and ${\gamma }_B$ from 0 to 1 in steps of 0.1 to investigate their influence on the PBG and the bandwidths of the TES. Figure 2d shows the PBG width as a function of ${\gamma }_A$ and ${\gamma }_B$. As ${\gamma }_A$ increases, the PBG initially decreases and then increases, corresponding to the band gap closing at the Dirac point followed by band inversion. Before band inversion, increasing ${\gamma }_B$ monotonically widens the PBG. Therefore, to maximize the PBG, one can choose a small ${\gamma }_A$ and a large ${\gamma }_B$.The width of the PBG directly determines the upper limit of the operational bandwidth and the transmission stability of the topological edge states [37]. We further analyze the dependence of the TES band structures on ${\gamma }_A$ and ${\gamma }_B$. For fixed ${\gamma }_B$=0.5 (${\gamma }_A$=0.25), Figure 2e shows that increasing ${\gamma }_A$ shifts the central frequencies of both TES1 and TES2 upward, with TES2 shifting more significantly, leading to band overlap or even inversion when ${\gamma }_A$>0.2. Conversely, for fixed ${\gamma }_A$=0.5, Figure 2f indicates that ${\gamma }_B$ has a weak effect on TES1 but raises the central frequency of TES2 and broadens its bandwidth; however, the bandwidth shrinks markedly when ${\gamma }_B$>0.5. To maximize the operational bandwidth while minimizing band overlap, we identify the optimal parameter range as ${\gamma }_A$<0.2 and 0.5<${\gamma }_B$<0.6. The final chosen values are ${\gamma }_A$=0.175 and ${\gamma }_B$=0.525, yielding the band structure shown in Figure 2g. The overall relative band gap width reaches 17.8%, a 40.6% improvement over Ref. [34]. TES1 operates from 169.2 to 184.5 THz (relative bandwidth 8.65%), and TES2 from 184.7 to 201 THz (relative bandwidth 8.45%), with a 0.2 THz isolation gap. Each bandwidth is increased by approximately 0.3 THz compared to the initial design, effectively suppressing disorder-induced scattering between edge states while preserving the original bandwidth.

3. Results and Discussion

Based on the characteristics of the TES discussed above, we design and analyze a topological beam splitter (BS) as the fundamental building block for all-optical logic functions. The structure of the BS is shown in Figure 3a, and the corresponding electric field distribution at 193.5 THz is presented in Figure 3b. The blue and green regions represent VPC1 and VPC2, respectively. The yellow dashed line marks the transmission path along interface II (supporting TES2), while the black dashed line indicates interface I (supporting TES1). Circularly polarized light propagates in opposite directions on the two interfaces due to valley-spin locking. The yellow path forms a three-port waveguide structure. In terms of port configuration, Ports 1, 3, and 4 are designed to excite TES2, whereas Port 2 excites TES1. The operational frequency band is chosen as 185–201 THz, which lies within the TES2 band; therefore, Port 2 theoretically does not participate in the device function. Both the main waveguide and the two branch waveguides incorporate 60° bends. The Z-shaped waveguide exhibits no significant performance degradation, as shown in Figure 3c. In the frequency range 190.5–199 THz, the forward transmittance of a straight waveguide remains above 90%, while backscattering is below 5%. For the Z-shaped waveguide, the forward transmittance exceeds 80% over 189.2–199.8 THz. At the operating frequency of 193.5 THz, the transmittances reach 92.3% and 89.5%, respectively, confirming that light is tightly confined to the topological interface and propagates unidirectionally. When right-handed circularly polarized (RCP) light is launched into Port 4, it couples at the junction into the two output branch waveguides, Ports 1 and 3, thus realizing the beam splitting function.

We performed power scanning and quantitative monitoring for each port within the 185–201 THz frequency range. As shown in Figure 3d, we present the curves of power variation with frequency for the input port (Port 4) and the two output ports (Ports 1 and 3). Throughout the entire monitored band, the power values at Ports 1 and 3 are strictly consistent with a relative error of ≤ 0.01%, each accounting for half of the total power in the main waveguide—confirming that the device achieves precise 50:50 beam splitting across the entire band. At the operating frequency of 193.5 THz, the total transmittance of the system reaches 96.4%.

The insertion loss (IL) of the beam splitter, calculated as$IL=10{log}_{10}{\displaystyle \frac{P_{out}}{P_{in}}}$, is shown in Figure 3e. Over the range 189.2–197.4 THz, the IL remains below 0.5 dB, and at 193.5 THz it is as low as 0.21 dB. For comparison, conventional silicon-based photonic crystal beam splitters typically exhibit insertion losses between 0.4 and 2.5 dB. Even state-of-the-art topological splitters, such as the one reported in Ref. [38], show an insertion loss of 0.38 dB. The footprint of our device is 18.92 μm×17.87 μm, which can be further reduced if needed. These results highlight the compactness, broad bandwidth, and low loss of the proposed beam splitter.

It is worth noting that this beam splitter not only achieves a 50:50 equal power splitting but also has reciprocity and can further support stable on-chip interference functions: when signals are launched backward into the two branch waveguides, they interfere at the main waveguide junction. This feature lays the foundation for implementing optical logic functions on the same topological platform [6]. Using the BS configuration, we designate the two branch waveguides (Ports 1 and 3) as logic inputs A and B, and the main waveguide (Port 4) as the output Y, as shown in Figure 4a. The red stars on the two input waveguide paths indicate the positions of the simulated excitation sources. Within the TES2 operational band, left-handed circularly polarized (LCP) light propagates to the right and is defined as logic "1", while right-handed circularly polarized (RCP) light, which does not support rightward propagation, is defined as logic "0". Therefore, when an input port is excited by RCP light, the excitation source propagates to the left, which is functionally equivalent to a logic "0" input. The field distribution visible on the left side of the figure is the physical manifestation of this leftward propagation mode. Meanwhile, the backward scattering generated on the right side during leftward propagation simulates the actual output of the logic gate under the influence of backscattering. The output is considered logic "1" if the transmittance at Port 4 exceeds 70%, and logic "0" if it is below 30%.

Based on this, the OR gate is directly realized through the reciprocity of the beam splitter: if at least one of the inputs A or B is "1", the output Y is "1". The truth table and the corresponding field distributions at 193.5 THz are presented in Table 1 and Figure 4b-Figure 4e, respectively. In Figure 4b, the input state is "11" for the OR gate configuration, where there is no additional phase difference between the two input signals, resulting in an output of "1".

The XOR gate is implemented on the same structure by introducing phase control: a π phase shift (e.g., via a half-wave plate) is added at Port 3, so that the signal from input B arrives at the Y junction with a 180° phase difference relative to the signal from input A. When both inputs are "1", the equal-amplitude, out-of-phase signals interfere destructively, yielding output "0". When the inputs are different (01 or 10), a single input reaches the output without interference, resulting in "1". The truth table and field distributions at 193.5 THz are given in Table 1 and Figure 4c-Figure 4f, respectively. In Figure 4f, the input state is also labeled as "11", but this corresponds to the XOR gate configuration (with a π phase shift introduced at Port 3). The two out-of-phase signals interfere destructively, yielding an output of "0". Therefore, Figure 4b and Figure 4f correspond to different logic functions realized on the same physical structure under different phase configurations.

As shown in Figure 4g, the normalized output power for various logic states across the operational band confirms that the logic gates work correctly over the full monitored range. The extinction ratio (ER), a key figure of merit quantifying the contrast between logic "1" and "0", is defined as $ER=10{log}_{10}\left({\displaystyle \frac{P_1}{P_0}}\right)$, where P1 and P0 are the output powers for the "1" and "0" logic levels, respectively. The ER curves are plotted in Figure 4h. At the operating frequency of 193.5 THz, the OR gate exhibits an ER of 18.9 dB for the "10" and "01" input states and up to 24.9 dB for the "11" state. For the XOR gate, due to destructive interference, the output power for the "11" state is much lower than that for a logic "1", resulting in an ER as high as 44 dB. In contrast, for the "00" state, the output power is slightly higher due to residual backscattering, leading to a lower ER. These results demonstrate the excellent logic-level discrimination capability of the proposed logic gates.

Furthermore, a NOT gate can be realized using the same XOR gate structure by designating one input as a fixed auxiliary port. Specifically, input A is set as the auxiliary port and held at logic "1", while input B serves as the signal input. The operating principle again relies on interference: when input B is "0" (no signal), only the auxiliary signal reaches the output, giving Y = 1. When input B is "1", the two signals interfere destructively at the junction, yielding Y = 0. Since the NOT gate shares the identical physical structure with the XOR gate without introducing any additional components, its performance parameters are the same. The corresponding electric field distributions for the NOT gate can be found in Figure 4d and Figure 4f, corresponding to the "0→1" and "1→0" logic states, respectively.

To realize more complex logic functions, the basic gates (OR and XOR) can be cascaded. Taking the AND gate as an example, its logic expression can be written as A AND B=(A OR B) XOR (A XOR B). The implementation is shown in Figure 5a: an OR gate and an XOR gate are used as the first stage, with their inputs (Port 1 and Port 3) receiving the same logic signals. The phases are adjusted so that the two output signals have a 180° phase difference. These outputs are then fed into a second-stage XOR gate, realizing the AND function. Figure 5b–d depict the electric field distributions for the AND gate under different input logic states, where Figure 5b corresponds to input state “01”, Figure 5c to input state “11”, and Figure 5d to input state “00”. The complete truth table, excitation conditions, and output results for the AND gate are summarized in Table 2. With the demonstrated OR, XOR, NOT, and AND gates, further cascading can in principle construct all other logic gates, forming a complete set of all-optical logic units.

The transmittance and extinction ratio curves of the AND gate are depicted in Figure 6. Within the monitored frequency range of 186–200 THz, the cascaded AND gate yields a normalized output transmittance stably above 70% only when both inputs are logic '1', reaching 71.7% at the central operating frequency of 193.5 THz, while the transmittance remains below 10% for all other input states, consistent with the preset logic criteria. At 193.5 THz, the extinction ratio of the cascaded AND gate exceeds 30 dB for the '11/00' state and is higher than 15 dB for other logic states. Within the core operating bandwidth of 189.2–197.4 THz, the device extinction ratio is consistently above the practical threshold of 10 dB, fully verifying the excellent logic scalability and performance robustness of the proposed topological platform.