The Dimensionality Gap: Three Scaling Barriers to AGI on Von Neumann Architectures, and a Path Forward Through Neuromorphic-Photonic Substrates

1. Introduction

The dominant research paradigm in AGI pursues scale: larger transformer models, more GPU hours, bigger datasets. This approach has produced remarkable capabilities—large language models that pass professional examinations, generate code, and engage in extended reasoning [1,2]. The implicit assumption is that these capabilities will converge on general intelligence as scale increases.

We argue that this assumption contains a structural flaw. The biological brain, the only known system that achieves general intelligence, differs from silicon processors not merely in degree but in kind. The brain is a three-dimensional, asynchronous, event-driven graph with ∼86 billion neurons [3], each connecting to ∼7,000 others [4], operating at ∼20 W total [5]. Contemporary CPUs and GPUs are two-dimensional, globally clocked, memory-bottlenecked fetch-execute machines. The mismatch between these architectures is not a quantitative gap that Moore’s law can close—it is a dimensionality gap: a structural incompatibility between the topology, parallelism model, and energy budget of biology and those of planar silicon.

This paper makes two contributions. First, we formalise the dimensionality gap as three scaling barriers (Propositions 1–3)—lower bounds on the communication, memory bandwidth, and energy costs of emulating a brain-scale neural graph on von Neumann hardware. These bounds are derived from first principles of VLSI theory, memory architecture, and thermodynamics, and are evaluated at biological parameters. They establish that brain-scale emulation on 2D silicon is not merely expensive but infeasible at any realistic engineering timescale—the resource requirements exceed current technology by factors of ${10}^2$–${10}^3$ and improve only polynomially with process advances.

Second, we propose a constructive path forward: a hybrid neuromorphic–photonic architecture that addresses each barrier directly. Three-dimensional neuromorphic silicon restores the topological routing freedom lost in 2D fabrication (addressing Barrier 1). Integrated photonic interconnects provide the fan-out bandwidth and energy efficiency that electronic wires cannot (addressing Barriers 2 and 3). We specify quantitative targets for a first-generation device and identify the critical technology gaps.

We emphasise what this paper does not claim. It does not claim that brain emulation is sufficient for AGI—consciousness, grounding, and embodiment may require more. It does not claim that current deep learning is on the wrong track—transformer-based systems have genuine and remarkable capabilities that may not require brain-like hardware. It claims only that the specific path of “emulate the brain on GPUs” runs into three formal barriers that scaling alone cannot overcome, and that a different class of substrate is needed to make that path viable.

Related work.—The von Neumann bottleneck was identified by Backus in 1977 [12]. Neuromorphic computing was proposed by Mead in 1990 [13]. Modha et al. [15] and Davies et al. [14] have built large-scale neuromorphic chips. Shen et al. [17] demonstrated optical neural networks. Marković et al. [18] surveyed physics-based computing for AI. Our contribution is the formal quantification of the three barriers and the specific hybrid architecture that addresses all three simultaneously.

2. The Brain as a Computational Graph

We model the brain as a directed weighted graph $G=(V,E,w)$ with $\left|V\right|=N\approx 8.6\times {10}^{10}$ neurons [3], $\left|E\right|\approx {10}^{14}$ synaptic connections [4], and continuously variable synaptic weights $w:E\to \mathbb{R}$. Each vertex $v\in V$ fires asynchronously when a threshold function over its weighted inputs is exceeded—a non-linear, analog, event-driven computation.

Three properties of G are computationally critical:

Non-planarity.—G is embedded in three-dimensional space and exploits all three dimensions for wiring. It is highly non-planar: the cortical white matter consists of ∼150,000 km of myelinated axons [7] carrying long-range connections that cross every conceivable 2D section. The crossing number of a random graph with N vertices and average degree F scales as $\Omega (N^2·F^2/{log}^{2}N)$ when forced into a 2D embedding [8]. This non-planarity is not incidental; it enables the small-world connectivity (∼6 synaptic hops between any two neurons [9]) that underpins rapid information integration.

Massive fan-out.—The average neuron projects to $F\approx 7,000$ postsynaptic targets [4]. When a neuron fires, all F downstream neurons receive input simultaneously via physical axonal branching—a parallel broadcast at the speed of axonal propagation, with no serialisation.

Extreme energy efficiency.—A single synaptic transmission consumes ∼1–10 fJ [6]. The entire brain achieves ∼${10}^{14}$ synaptic operations per second at ∼20 W—an energy cost of ∼0.2 pJ per operation including all metabolic overhead [5,6].

3. Three Scaling Barriers

We now derive three lower bounds on the cost of emulating G on von Neumann hardware. Each barrier arises from a different axis of the dimensionality gap: topology, parallelism, and energy.

3.1. Barrier 1: Communication Complexity

Contemporary processors are fabricated as 2D planar silicon dies. Inter-unit communication must be routed on a flat surface. The fundamental constraint is the bisection bandwidth: the maximum data rate across any cut that partitions the chip into two halves of equal compute. For a 2D chip of area A, the bisection bandwidth scales as $\mathcal{O}\left(\sqrt{A}\right)$—the perimeter of the bisection line [19,20].

The brain’s graph G, by contrast, exploits three-dimensional wiring. The bisection bandwidth of a 3D-embedded graph with N nodes scales as $\mathcal{O}\left(N^{2/3}\right)$ [20], which for a 2D chip with the same node count drops to $\mathcal{O}\left(N^{1/2}\right)$. The ratio represents data movement that cannot be handled in-plane and must be serialised through the 2D bisection.

Proposition 1 

(Communication complexity barrier). Any 2D substrate emulating one timestep of a neural graph G with N vertices, average degree F, and 3D bisection bandwidth $B_{3D}=\Theta \left(N^{2/3}\right)$ must perform at least

$$C=\Omega \left({\displaystyle \frac{N^{2/3}·F}{N^{1/2}}}\right)=\Omega \left(N^{1/6}·F\right)$$

(1)

additional data-movement operations per timestep beyond what a 3D substrate would require, where the $N^{1/2}$ denominator is the 2D bisection bandwidth.

The derivation (Methods, §Section 3.1) follows from the bisection bandwidth framework of Thompson [19] and Leighton [20]. At brain parameters ($N=8.6\times {10}^{10}$, $F=7,000$), the overhead factor is

$$C\approx {(8.6\times {10}^{10})}^{1/6}\times 7,000\approx 660\times 7,000\approx 4.6\times {10}^6$$

(2)

additional data movements per emulated neuron per timestep. Across the ∼${10}^{10}$ neurons that fire per second (at average ∼10 Hz firing rate across ${10}^{11}$ neurons active at any moment, with sparse coding), this amounts to ∼$4.6\times {10}^{16}$ excess data movements per second—orders of magnitude beyond the ∼${10}^{12}$ cache-line transfers per second achievable on current high-end GPUs [21].

Interpretation.—This barrier does not claim that 2D emulation is impossible in principle. It establishes that the communication overhead grows as $\Omega \left(N^{1/6}·F\right)$ and cannot be eliminated by algorithm design; it is a property of the dimensional mismatch between the graph and the substrate. Process scaling (smaller transistors) increases $N^{1/2}$ slowly and does not close the gap.

3.2. Barrier 2: Serialisation Bandwidth

When neuron v fires in the brain, it updates F downstream neurons simultaneously via axonal branching. On a von Neumann machine, this fan-out must be serialised: F sequential (or SIMD-batched) memory writes. The required aggregate memory bandwidth is:

Proposition 2 

(Serialisation barrier). Any von Neumann emulation of a neural graph with N neurons, average fan-out F, and average firing rate f requires sustained memory bandwidth

$$B\ge N·f·F·b,$$

(3)

where b is the bytes per synaptic update (minimum: weight read + state write ≥ 8 bytes for 32-bit precision).

At biological parameters ($N=8.6\times {10}^{10}$, $f\approx 1$ Hz average across all neurons including quiescent populations [10], $F=7,000$, $b=8$ bytes):

$$B\ge 8.6\times {10}^{10}\times 1\times 7,000\times 8\approx 4.8\times {10}^{15}\mathrm{bytes}/\mathrm{s}.$$

(4)

This is approximately $4.8$ PB/s. For comparison, the NVIDIA H100 GPU achieves ∼3.35 TB/s HBM bandwidth [21]—a factor of ∼1,400 shortfall.

Even at a reduced firing rate estimate of 0.1 Hz (accounting for sparse cortical activity [11]), the requirement is ∼480 TB/s—still ∼140× current GPU bandwidth. Memory bandwidth has historically improved at ∼25%/year, giving a ∼20–30 year timeline to close a $140\times$ gap on this axis alone, assuming current architectural paradigms.

Counterargument and response.—One might object that sparse firing patterns reduce the effective bandwidth. This is already accounted for: the 0.1–1 Hz average rate reflects cortical sparsity. The deeper issue is that even sparse updates are scatter-pattern memory accesses (each firing neuron writes to F non-contiguous memory locations), which achieve only ∼1–10% of peak bandwidth on GPU memory systems [22]. The effective bandwidth gap is therefore 10–$100\times$ larger than the raw numbers suggest.

3.3. Barrier 3: Energy Scaling

Proposition 3 

(Energy barrier). Silicon emulation of a neural graph with synaptic throughput S operations/s at per-operation energy ${\eta }_{\mathrm{Si}}$ requires power

$$P_{\mathrm{Si}}=S·{\eta }_{\mathrm{Si}}.$$

(5)

At brain-scale throughput $S\approx {10}^{14}$ ops/s and current GPU efficiency ${\eta }_{\mathrm{Si}}\approx 60$ pJ/op (NVIDIA H100 achieves ∼60 pJ per 16-bit multiply-accumulate at the chip level [21,23]), the required power is

$$P_{\mathrm{Si}}\approx {10}^{14}\times 6\times {10}^{-11}\approx 6\times {10}^3\mathrm{W}=6\mathrm{kW}\mathrm{per}\mathrm{chip}\mathrm{equivalent}.$$

(6)

Accounting for memory access energy (∼10× the compute energy for off-chip DRAM access at brain-scale working sets [23]), the system-level power is ∼60 kW–6 MW, versus ∼20 W for the biological brain.

The energy ratio ${\eta }_{\mathrm{Si}}/{\eta }_{\mathrm{brain}}\approx 60\mathrm{pJ}/0.2\mathrm{pJ}=300$ quantifies the efficiency gap. This ratio has improved at approximately $2\times$ per chip generation (∼3 years), or ∼25%/year—similar to the Dennard scaling rate, which ended circa 2006 [24,25]. Post-Dennard, energy efficiency gains have slowed to ∼10–15%/year. At 15%/year, closing a $300\times$ gap requires ∼40 years.

Thermodynamic context.—The Landauer limit for irreversible bit erasure is $k_{B}Tln2\approx 3\times {10}^{-21}$ J at room temperature [26]. Current CMOS operates at $\sim {10}^4$–${10}^5\times$ Landauer, while biological synapses operate at $\sim {10}^2$–${10}^3\times$ Landauer. Biology is not at the fundamental limit either, but it is ∼100× closer than silicon. This suggests that the energy gap has both an engineering component (improvable) and a physical-substrate component (requiring new materials or mechanisms).

4. Quantitative Comparison

Table 1 summarises the dimensionality gap across eight metrics for five systems: the biological brain, a current CPU, a current GPU, a state-of-the-art neuromorphic chip, and the proposed hybrid architecture of Section 5.3.

Several features of Table 1 deserve comment. The brain exceeds all silicon systems in neuron count, connection count, and energy efficiency by orders of magnitude. Current neuromorphic chips (Loihi 2, IBM NorthPole [15]) close the energy-per-operation gap to ∼50× and achieve asynchronous operation, but remain 2D planar and orders of magnitude short of brain-scale node counts. No existing system addresses all three barriers simultaneously. The hybrid architecture (Section 5.3) is the first proposal that targets all eight dimensions concurrently.

5. A Path Forward

The three barriers identify the axes along which a brain-scale substrate must improve. We now propose three complementary technologies, culminating in a hybrid architecture.

5.1. 3D Neuromorphic Hardware

Barrier 1 arises from 2D fabrication. The remedy is 3D integration: stacking compute layers vertically so that connections can exploit all three spatial dimensions, partially recovering the routing freedom of biological tissue.

The technology exists in embryonic form. High-Bandwidth Memory (HBM) stacks up to 12 DRAM layers with through-silicon vias (TSVs) [27]. Monolithic 3D integration, where transistor layers are fabricated sequentially on a single wafer [28], promises >100 vertical connections per $\mu {\mathrm{m}}^2$—far denser than TSV-based stacking.

A brain-scale 3D neuromorphic chip would require: (i) at least 10–100 vertical compute layers, each containing ∼${10}^7$–${10}^8$ neuromorphic cores; (ii) asynchronous, event-driven operation with no global clock; (iii) on-chip analog or mixed-signal synaptic weight storage to avoid the memory-access energy penalty of digital SRAM/DRAM.

Intel Loihi 2 [14] and IBM NorthPole [15] implement (ii) and partially (iii) in 2D. BrainScaleS-2 [29] uses analog circuits for synaptic dynamics. None has achieved (i). Monolithic 3D integration [28] is the most promising path to vertical scaling, but thermal management at >10 layers remains an open engineering challenge.

5.2. Photonic Interconnects

Barriers 2 and 3 arise from the serialisation cost and energy dissipation of electronic interconnects. Photonic (optical) communication offers three properties that directly address these:

Parallel broadcast.—A single optical waveguide carrying W wavelengths via wavelength-division multiplexing (WDM) can broadcast to W destinations simultaneously, providing physical fan-out without serialisation. At $W=100$ channels per waveguide (achievable with current silicon photonics [30]), each waveguide replaces 100 electronic wires.

Low energy.—Optical switching in microring resonators achieves ∼1–10 fJ per bit [30,31], approaching the synaptic energy of biology.

No crosstalk.—Photons do not interact with each other in linear media, enabling dense waveguide routing without the signal integrity problems of electronic interconnects at high density.

Optical neural networks have been demonstrated by Shen et al. [17] using Mach–Zehnder interferometer meshes, and photonic tensor cores by Feldmann et al. [31] using phase-change materials. The critical gap is optical memory: current photonic systems rely on electronic memory for weight storage, creating an optical–electronic conversion bottleneck. Until all-optical or hybrid opto-electronic memory matures, photonic systems are best suited for the communication layer (fan-out and long-range routing) rather than the compute layer (synaptic weight storage and integration).

5.3. Hybrid Neuromorphic–Photonic Architecture

We propose a hybrid architecture that assigns each technology to the task it handles best:

Electronic neuromorphic cores handle local synaptic computation: weight storage, dendritic integration, spike generation. These are fabricated as 3D-stacked layers of asynchronous, mixed-signal neuromorphic circuits (Section 5.1), providing the topology and energy density needed for local processing.

Photonic interconnects handle long-range communication: high-fan-out spike broadcast between cores on different layers or at large intra-layer distances. WDM waveguides integrated between neuromorphic layers provide the bandwidth of Barrier 2 at the energy cost of Barrier 3.

Architecture specification:

• Compute:≥${10}^9$ neuromorphic neurons across ≥10 vertically stacked layers, with on-chip analog synaptic weights.
• Interconnect: Integrated silicon photonic waveguides with ≥100 WDM channels per waveguide, providing aggregate fan-out bandwidth ≥${10}^{14}$ events/s.
• Energy:≤5 pJ per synaptic operation (electronic compute + photonic communication), system power ≤500 W at ${10}^9$-neuron scale.
• Timing: Fully asynchronous—no global clock.

This architecture addresses each barrier: 3D stacking reduces the communication overhead of Barrier 1 by restoring $\mathcal{O}\left(N^{2/3}\right)$ bisection bandwidth; photonic fan-out eliminates the serialisation of Barrier 2 by providing physical parallel broadcast; and the combination of analog neuromorphic compute (∼1–10 pJ/op) and photonic communication (∼1–10 fJ/bit) approaches the energy budget of Barrier 3.

The first-generation device targets ${10}^9$ neurons—approximately 1% of brain scale. This is sufficient to emulate a complete cortical column or a small mammalian brain (mouse-scale), providing a biologically meaningful testbed. Scaling to ${10}^{11}$ (full human brain) requires ∼100× more layers or lateral area, which we regard as a second-generation challenge contingent on advances in monolithic 3D integration and thermal management.

6. Limitations and Scope

Brain emulation is not sufficient for AGI.—The three barriers concern the feasibility of brain-scale emulation on von Neumann hardware. They do not address whether emulation is sufficient for general intelligence. Consciousness, embodied cognition, developmental learning, and social grounding may require mechanisms beyond what any hardware substrate provides.

Current deep learning may not need brain-like hardware.—Large language models achieve impressive capabilities on conventional GPUs without brain-like connectivity. Our argument does not claim that GPU-based AI is a dead end—only that the specific path of “scale up brain emulation on GPUs” encounters formal barriers. Alternative paths to AGI (e.g., via scaling transformers, symbolic-neural hybrids, or novel algorithms) are not addressed by our analysis.

The barriers are lower bounds, not impossibility proofs.—Each proposition establishes a minimum resource requirement, not an absolute impossibility. A sufficiently large GPU cluster could, in principle, brute-force past Barriers 1–3. The argument is that the required cluster size (∼${10}^4$–${10}^6$ current GPUs, consuming megawatts) is impractical and that a purpose-built substrate is the more viable path.

The proposed architecture is speculative.—The hybrid neuromorphic–photonic architecture of Section 5.3 specifies targets, not a demonstrated system. Key technology gaps remain: monolithic 3D integration at >10 layers, large-scale photonic–electronic co-integration, thermal management of 3D stacks, and scalable fabrication. We present it as a research direction, not a product roadmap.

The brain may not be optimal.—We use the brain as a benchmark because it is the only known generally intelligent system, not because we claim its architecture is optimal. Alternative substrates (quantum, chemical, biological) may achieve general intelligence through entirely different mechanisms.

7. Conclusion

The question animating this paper is not “How many more GPUs do we need?” but “Are GPUs the right substrate at all?” The three scaling barriers—communication complexity, serialisation bandwidth, and energy—establish that the answer is no, at least for the brain-emulation path to AGI. The dimensionality gap between 2D silicon and 3D biology is structural, not quantitative, and it improves only polynomially with process scaling.

The hybrid neuromorphic–photonic architecture we propose is not a finished solution. It is a specification of what a brain-scale substrate must look like: three-dimensional, asynchronous, massively parallel, with photonic long-range communication and analog local computation. Building it is an engineering challenge at least as ambitious as the Manhattan Project or the Human Genome Project. But the scaling barriers suggest it is a challenge that cannot be bypassed—only met.