Submitted:
31 October 2025
Posted:
03 November 2025
You are already at the latest version
Abstract
Keywords:
1. Introduction
2. Design Framework for Human-Machine Collaborative Anti-Money Laundering Systems
2.1. Overall Design Approach
2.2. Functional Module Division
2.3. Collaborative Operation Logic
3. Technical Methods and Model Construction
3.1. Multi-Armed Scenario-Based Bandit Alert Routing Mechanism
3.2. Active Learning-Driven Sample Selection
3.3. Explainable Artificial Intelligence (XAI) Design

4. Experimental Design and Results Analysis
4.1. Data Sources and Processing
4.2. Experimental Design and Control Configuration
4.3. Experimental Results and Analysis
4.3.1. Suspicious Transaction Detection Efficiency
4.3.2. Accuracy and Resource Consumption Performance
4.3.3. Compliance and Explainability
5. Conclusions
References
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| Module/Role | Reference Device Model | Technology Stack/Description |
|---|---|---|
| Data Acquisition and Preprocessing | Dell PowerEdge R650xs (CPU Node) | Apache Kafka 3.x/Schema Registry; Dual power supplies, NVMe system disk |
| Feature and Account Profile Storage | Dell PowerEdge R760 (CPU Node) | Apache Flink 1.18/Redis Cluster/Parquet Lakehouse |
| Alarm Generation Module | Dell PowerEdge R760 | Rule Engine/gRPC Inference Gateway |
| Bandit Traffic Routing and Orchestration Module | Dell PowerEdge R760 | Ray Serve/Policy Storage/SLA Orchestrator |
| Machine Learning Training and In-Service Learning | Dell PowerEdge R760xa + NVIDIA A100 80GB | PyTorch/XGBoost; CUDA 12; Mixed-Precision Computing |
| Model Service Module | Dell PowerEdge R760xa + A100 80GB | Triton Inference Server; Low-latency batch/stream inference |
| Narrative-Level Explainability Module | Dell PowerEdge R760 | SHAP/Counterfactual Explanations + Knowledge Graph |
| Security auditing and key management | Thales Luna HSM 7 | FIPS 140-2 Level 3; Digital Signatures and Timestamps |
| Storage Module | NetApp AFF A400 | Snapshot/WAFL; Compliance-Compliant Write-Once Read-Many Policy |
| Network Module | Arista 7050X3 | 25/100 GbE Spine-Leaf architecture; RoCEv2 support |
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