preprints.org > engineering > electrical and electronic engineering > doi: 10.20944/preprints202311.1169.v1

Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Version 1 : Received: 16 November 2023 / Approved: 17 November 2023 / Online: 21 November 2023 (03:53:06 CET)

This study presents the design and implementation of a PLC microprocessor adhering to the IEC-61131-3 standard, executed on a Cyclone-V FPGA using a DE10-NANO development board. Our microprocessor optimizes the central processing unit by streamlining the data path, achieving a remarkable simulated response time of approximately 60 ns, equivalent to three clock cycles at a 50MHz frequency for Boolean operations. To substantiate our approach, we conducted practical experiments utilizing a FESTO conveyor station, employing relays as actuators, and incorporating optical and inductive sensors. The results underscore the feasibility of our proposed approach and serve as practical validation of its efficacy. This work introduces a promising avenue for the development of cost-effective PLCs employing SoC FPGA variants. Additionally, a thorough comparison of execution times with other early reported architectures. Our microprocessor outperforms even well-established PLCs like the S7-312, with substantial reductions in execution times of 94.54% for floating-point operations, 71.42% to 93.33% for word operations, and up to 78.57% for bit operations.

Architecture design, FPGA, IEC 61131-3, low-latency, PLC, System-on-Chip

Engineering, Electrical and Electronic Engineering

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