preprints.org > engineering > electrical and electronic engineering > doi: 10.20944/preprints202306.0577.v1

Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Version 1 : Received: 7 June 2023 / Approved: 8 June 2023 / Online: 8 June 2023 (03:39:58 CEST)

As the PCIe 6.0 specification places higher requirements on signal integrity and transmission la-tency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuit as a key component of high-speed serial interface, its delay and jitter size directly affect the overall performance of PCIe. For the conventional Retimer circuit with large latency and low jitter performance, this paper proposes a low latency and low jitter Retimer circuit based on CDR+PLL architecture for PCIe 6.0, using a jitter canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data; The data is sampled using the retiming clock and then output, avoiding the problem of large penetration latency of con-ventional Retimer circuits. The circuit is designed using CMOS 28nm process. Simulation results show that when 112Gbps PAM4 data is input to the Retimer circuit, the Retimer penetration la-tency is 27.3 ps, which is 83.5% lower than the conventional Retimer structure; the output data jitter is 741 fs, a 31.4% reduction compared to the conventional Retimer structure.

PCIe 6.0; SerDes; low latency,; low jitter; Retimer

Engineering, Electrical and Electronic Engineering

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