Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

ASMD-FSMD Technique for Designing Digital Devices on FPGA

Version 1 : Received: 1 October 2020 / Approved: 2 October 2020 / Online: 2 October 2020 (13:54:34 CEST)

How to cite: Salauyou, V. ASMD-FSMD Technique for Designing Digital Devices on FPGA. Preprints 2020, 2020100043 (doi: 10.20944/preprints202010.0043.v1). Salauyou, V. ASMD-FSMD Technique for Designing Digital Devices on FPGA. Preprints 2020, 2020100043 (doi: 10.20944/preprints202010.0043.v1).

Abstract

Recently, there has been, on the one hand, an increase in the complexity of digital device designs and, on the other hand, an increase in the requirements for the development time and the reliability of the designs. One of the directions of solving this problem is developing new techniques for designing digital devices.This paper proposes a new technique for designing digital devices based on finite state machines with datapath (FSMD), when the functioning of the device is described in the form of an algorithm state machine with datapath (ASMD) charts. The new technique is called ASMD-FSMD. Different digital device design techniques are compared to each other using design examples of a synchronous multiplier on field programmable gate array (FPGA). The efficiency of the ASMD-FSMD technique compared to the traditional approach in terms of area and performance was investigated. The ASMD-FSMD technique, compared to the traditional one, reduces the area from 28.6% to 39.7% and increases the speed for some designs to 17.6%. In addition, using the ASMD-FSMD technique significantly reduces design time and increases design reliability. In conclusion, recommendations for using the ASMD-FSMD technique are made.

Subject Areas

digital device; finite state machine with datapath; algorithm state machine with datapath; field programmable gate array; design technique; development time; reliability; area; performance

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