Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

# An Efficient FPGA-based Frequency Shifter for LTE/LTE-A Systems

Version 1 : Received: 28 June 2019 / Approved: 1 July 2019 / Online: 1 July 2019 (11:52:58 CEST)

How to cite: Pereira de Figueiredo, F.A. An Efficient FPGA-based Frequency Shifter for LTE/LTE-A Systems. Preprints 2019, 2019070011 (doi: 10.20944/preprints201907.0011.v1). Pereira de Figueiredo, F.A. An Efficient FPGA-based Frequency Shifter for LTE/LTE-A Systems. Preprints 2019, 2019070011 (doi: 10.20944/preprints201907.0011.v1).

## Abstract

The Physical Random Access Channel (PRACH) plays an important role in LTE and LTE-A systems. It is through the PRACH channel that the user equipment (UE), based on eNodeB's timing estimates, aligns its uplink transmissions to the eNodeB's uplink and gain access to the network. One of the initial operations executed by the PRACH receiver at eNodeB side is the translation of the PRACH signal back to base band, $i.e.$, center the PRACH signal around DC. This operation is a necessary step for preamble detection and can be carried out through a time-domain frequency shift operation. Therefore, in this paper we present the hardware architecture and implementation details of a configurable and optimized FPGA-based time-domain frequency shifter. It is a hardware-efficient and accurate architecture for converting the relevant received PRACH signal into base band before further signal processing. The architecture is manly based on a customized Numerically Controlled Oscillator (NCO), which is used for generating complex exponentials employing only adders, a Look-Up Table (LUT) and plain logic resources. The main advantage of the proposed hardware architecture is that it completely eliminates the need for storing a large number of long complex exponential sequences by employing a single LUT and exploiting quarter wave symmetry of the basis waveform. Our simulation results show that the proposed customized NCO architecture provides high Spurious Free Dynamic Range (SFDR) signals using a minimal amount of FPGA resources. Moreover, the proposed architecture exhibits spur-suppression ranging from 62.13 to 153.58 dB without using Taylor Series correction.

## Subject Areas

LTE, LTE-A, 4G, PRACH, NCO, time-domain frequency shift, FPGA

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