Preprint Article Version 1 This version is not peer-reviewed

How to Test, Analyze, and Reduce Memory Interference Delay in Modern COTS Multicore Systems?

Version 1 : Received: 12 September 2018 / Approved: 12 September 2018 / Online: 12 September 2018 (15:48:39 CEST)

How to cite: Msadek, N. How to Test, Analyze, and Reduce Memory Interference Delay in Modern COTS Multicore Systems?. Preprints 2018, 2018090223 (doi: 10.20944/preprints201809.0223.v1). Msadek, N. How to Test, Analyze, and Reduce Memory Interference Delay in Modern COTS Multicore Systems?. Preprints 2018, 2018090223 (doi: 10.20944/preprints201809.0223.v1).

Abstract

In modern Commercial Off-The-Shelf (COTS) multicore systems, cores can produce several simultaneous memory requests. The processing of such requests over the memory controller negatively impacts the interference delay triggered by running parallel tasks on the platform. In this paper, we propose a software-based testing approach for analyzing memory interference delay, when cores are exposed to extensive read/write requests that access in parallel their Cache Coherent Interconnect. The hardware targeted in this work is the well-known LayerScape QorIQ LS2085A, which can be approached as a potential successor to the Freescale QorIQ P4080. The test analysis was conducted based on a bare-metal operating system that we developed to guarantee a deterministic execution environment at all time points. Our testing was accomplished using a set of carefully designed synthetic benchmarks as well as TACLeBench benchmarks.

Subject Areas

Memory Delay; Multicore Systems; Interference Delay; Real-Time Systems; Testing

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