LOCATE: Learning-Based Localization of Obfuscated FSM State Registers via Timing and Switching-Activity Fingerprints

1. Introduction

Finite-state machines (FSMs) are fundamental components of digital systems and are widely used to implement control-oriented functions such as protocol management, sequencing, arbitration, and system coordination. Because the state transitions of an FSM directly determine the behavior of the underlying control logic, recovering the FSM can reveal important information about the functionality and operation of a design. Consequently, FSMs represent an important target for intellectual property (IP) protection, particularly when integrated circuits are exposed to untrusted manufacturing, testing, or reverse-engineering environments [1,2,3,4].

Several hardware-security techniques have been proposed to protect FSM implementations against unauthorized analysis. FSM obfuscation modifies the original state space, transition behavior, or encoding of an FSM to make reconstruction of the intended state-transition graph more difficult [3,4,5]. Such techniques can introduce additional states, transitions, key-dependent behavior, or other modifications intended to conceal the original functionality. The security of these techniques is generally evaluated according to the difficulty of recovering the protected FSM behavior or determining the correct functional configuration.

However, protecting the logical behavior of an FSM does not necessarily eliminate information introduced during synthesis and implementation. State registers participating in an obfuscated FSM (OFSM) remain interconnected with the combinational logic implementing the corresponding next-state and control functions. These implementation characteristics can influence measurable properties of individual flip-flops, including their timing behavior and switching activity. Consequently, OFSM state registers may exhibit statistical characteristics that distinguish them from other sequential elements even when explicit structural information about the FSM is unavailable.

Motivated by this observation, this work investigates whether state registers in ProtectIP-obfuscated FSM implementations can be localized using only implementation-level timing and switching-activity information. Identifying these registers would not, by itself, recover the original FSM or defeat the obfuscation mechanism. Nevertheless, accurately localizing the state registers associated with the protected FSM can significantly reduce the set of sequential elements that must be considered during subsequent reverse-engineering or security analysis. This implementation-level distinguishability therefore represents a potential source of information leakage that should be considered when evaluating the security of FSM-obfuscation techniques.

To investigate this leakage, we construct a numerical profile for each flip-flop using three implementation-level features: setup timing, hold timing, and switching activity. Our analysis shows that OFSM registers exhibit distinguishable timing and activity characteristics across multiple benchmark circuits. In particular, the combination of setup and hold information provides substantial discriminatory capability, while switching activity supplies complementary information that further improves identification.

To quantify this leakage, we propose LOCATE, a machine-learning-based approach for localizing OFSM state registers, and evaluate it across six benchmark designs containing 4,743 flip-flops, of which 331 correspond to OFSM state registers. Under within-design five-fold validation, the approach correctly localizes 281 of the 331 OFSM registers while producing only 14 false positives, corresponding to 95.3% precision, 84.9% recall, and an F1 score of 89.8%. More importantly, leave-one-design-out (LODO) cross-design evaluation, in which the target circuit is completely excluded from training, achieves 87.2% precision, 80.4% recall, and an F1 score of 83.6%. These results demonstrate that a substantial portion of the observed timing and switching-activity fingerprint transfers to previously unseen protected circuits.

The overall attack scenario is illustrated in Figure 1. The adversary first constructs labeled ProtectIP-obfuscated training designs, extracts per-register timing and switching-activity features, and trains a localization model. The learned fingerprint is then applied to an unseen target design without requiring OFSM labels from that target.

The main contributions of this work are summarized as follows:

• We investigate implementation-level timing and switching activity as sources of information leakage for localizing OFSM state registers without relying on register names or explicit structural features.
• We characterize OFSM and non-OFSM registers across six ProtectIP-obfuscated benchmark designs and demonstrate recurring timing and switching-activity fingerprints.
• We develop LOCATE, a machine-learning-based OFSM register-localization approach, and demonstrate cross-design transferability using leave-one-design-out evaluation, achieving 87.2% precision, 80.4% recall, and an F1 score of 83.6% on previously unseen target circuits.
• We perform feature-ablation analysis showing that setup and hold timing provide the strongest combined discrimination, while switching activity contributes complementary information that further improves localization performance.

The remainder of this paper is organized as follows. Section II presents the background and related work. Section III defines the threat model and cross-design attack assumptions. Section IV describes the proposed OFSM register-localization methodology. Section V presents the experimental setup and evaluation results. Section VI discusses the security implications and limitations of the proposed attack. Finally, Section VII concludes the paper.

2. Background and Related Work

2.1. FSM-Based Hardware Obfuscation

Finite-state machines (FSMs) implement control behavior in a wide range of digital systems and are therefore attractive targets for hardware intellectual-property (IP) protection. Since the state and transition behavior of an FSM can reveal important information regarding the operation of a design, several hardware-obfuscation techniques have focused on modifying the state space or state-transition function to prevent unauthorized recovery of the original control behavior [3,4,5,6,7].

Early work on active hardware metering demonstrated that the state space of a design could be modified by introducing additional states and transitions such that the circuit becomes functional only after an appropriate activation sequence is applied [5]. HARPOON subsequently introduced an obfuscation-based SoC design methodology in which additional states are incorporated into the original FSM and a specific input sequence is required to transition the circuit from an obfuscated mode to its normal functional mode [3]. State-space obfuscation was later studied more broadly as a mechanism for protecting sequential circuits against IP piracy and tampering by modifying the state-transition function and introducing additional logic structures [7].

Rahman and Bhunia more recently presented a practical state-space obfuscation framework that considers scalability, integration with existing EDA flows, and robustness against emerging reverse-engineering attacks [4]. Rahman et al. further investigated state-space obfuscation through a red-team–blue-team methodology in which attacks and defenses are iteratively evaluated to identify and strengthen weaknesses in the protection mechanism [8]. Other recent approaches, such as ReTrustFSM, perform FSM obfuscation at the register-transfer level while combining an external key, cycle-dependent input behavior, and a concealed state-transition function [6].

The primary security objective of these techniques is to prevent an adversary from recovering the original state-transition graph (STG), determining the correct activation sequence, or separating functional FSM behavior from the added obfuscation logic. However, logical obfuscation does not necessarily eliminate implementation-level characteristics introduced during synthesis, technology mapping, and timing optimization. Consequently, information associated with the implementation of protected state registers may remain observable even when the original FSM functionality is concealed.

2.2. Reverse Engineering and FSM Extraction

The effectiveness of FSM obfuscation depends strongly on the amount of information that can be recovered from the implemented circuit. Reverse-engineering research has demonstrated that structural information contained in synthesized gate-level netlists can reveal higher-level design information [9,10,11].

Fyrbiak et al. investigated the practical difficulty of FSM-based hardware obfuscation under realistic reverse-engineering capabilities [9]. Their work demonstrated that control-path information can be automatically extracted from third-party gate-level netlists and used to analyze, and in several cases circumvent, existing FSM-obfuscation schemes. These results highlight an important distinction between increasing the logical state space and preventing an adversary from identifying the structural implementation of the protected control logic.

Identifying FSM state registers is itself an important reverse-engineering problem. A synthesized design may contain hundreds or thousands of flip-flops implementing datapath registers, counters, pipelines, configuration registers, and control state. Determining which subset corresponds to an FSM can therefore represent an important step toward reconstructing its state-transition behavior [10].

FSMx-Ultra addresses this problem by extracting FSMs from highly unstructured gate-level netlists [10]. The framework converts the synthesized netlist into a graph representation and employs graph-theoretic and topological analysis to distinguish FSM state registers from other sequential elements. After identifying the state registers, the corresponding gate-level state-transition behavior can be reconstructed. This demonstrates that FSM state-register identification can remain feasible even after synthesis removes much of the structural information available in the RTL description.

Structural information has also been exploited directly against FSM-obfuscation techniques. Structural-analysis attacks have shown that information recovered from an obfuscated FSM can be transformed into constraints that assist in recovering secret information associated with the protection mechanism [12]. These studies demonstrate that the security of FSM obfuscation should be evaluated using information available from the implemented circuit rather than only the apparent complexity of the protected state space.

In contrast to these structurally driven approaches, the present work does not use explicit netlist connectivity, fan-in/fan-out relationships, feedback paths, or state-transition reconstruction for localization. Instead, it investigates whether implementation-level timing and switching-activity measurements alone reveal sufficient information to localize OFSM state registers.

2.3. Implementation-Level Information Leakage

Hardware implementations expose characteristics that are not necessarily represented explicitly in a circuit’s functional description [1]. Synthesis, technology mapping, and timing optimization transform RTL logic into interconnected standard cells and timing paths with measurable implementation-level properties. Similarly, the switching activity of sequential elements depends on the functional behavior and transition patterns of the surrounding logic [13].

For FSM state registers, these implementation characteristics are particularly relevant because the registers participate in a common control structure. Their inputs are determined by next-state logic, and their outputs influence subsequent state transitions and control decisions. As a result, registers belonging to the same protected FSM may exhibit statistically distinguishable implementation-level properties.

Existing gate-level reverse-engineering approaches have primarily exploited structural and topological properties of synthesized netlists [9,10,11,14]. Attacks on FSM-obfuscation schemes have similarly focused on structural analysis, state-transition reconstruction, and key recovery [9,12]. Recent work has also explored machine-learning-based attacks using structural representations of obfuscated sequential circuits [15].

Related work on logic obfuscation more broadly has demonstrated that structural information and oracle-guided analysis can expose protected functionality or secret configuration information [16,17].

In contrast, the present work investigates whether OFSM state registers can be localized using only implementation-derived numerical characteristics. Rather than reconstructing netlist topology or explicitly extracting the state-transition graph, the proposed approach uses setup timing, hold timing, and switching activity as per-register observables. The objective is therefore complementary to conventional FSM reverse engineering: determining whether implementation-level timing and activity alone provide sufficient information to distinguish OFSM state registers from other sequential elements.

2.4. Research Gap and Motivation

Prior work establishes two important observations. First, FSM obfuscation can protect control behavior by modifying the state space, transition function, and activation behavior [3,5,6,7]. Second, reverse engineering can recover substantial information about FSM implementations from structural characteristics of synthesized gate-level netlists [9,10,12].

These two research directions leave an important question: whether the implementation process itself creates measurable numerical fingerprints that reveal the registers associated with an obfuscated FSM without first requiring explicit structural FSM extraction.

This work addresses this gap by investigating OFSM register localization from setup timing, hold timing, and switching activity. The resulting analysis therefore examines a complementary source of implementation-level leakage that may remain observable despite logical FSM obfuscation.

3. Threat Model and Reverse-Engineering Objective

We consider designs protected using the ProtectIP state-space obfuscation methodology proposed by Rahman and Bhunia [4]. The adversary’s objective is to localize the flip-flops associated with the resulting obfuscated finite-state machine (OFSM) within the complete set of sequential elements of the target design.

The adversary does not attempt to recover the original FSM state-transition graph, determine the secret key, or reconstruct the complete functionality of the protected circuit. Instead, the objective is OFSM register localization, i.e., reducing the set of candidate flip-flops that may correspond to the protected state machine.

The adversary is assumed to have access to register-level implementation information obtained from a timing and activity analysis environment. For each flip-flop, three numerical measurements are available: setup timing, hold timing, and switching activity. These measurements constitute the observable feature set used by the proposed attack. Register names, designer annotations, and prior knowledge of the target OFSM-register identities are not assumed to be available. Furthermore, explicit structural information, including fan-in/fan-out connectivity, feedback paths, logic-cone characteristics, and state-transition relationships, is not used for localization.

For a flip-flop $F{F}_i$, the adversary observes the feature vector

$${\mathbf{x}}_i=[S_i,H_i,T_i],$$

(1)

where $S_i$, $H_i$, and $T_i$ denote the setup-timing, hold-timing, and switching-activity measurements, respectively.

Given a target design containing N flip-flops,

$$\mathcal{F}=\{F{F}_1,F{F}_2,\dots ,F{F}_N\},$$

(2)

the adversary seeks to identify a subset

$${\widehat{\mathcal{F}}}_{\mathrm{OFSM}}\subseteq \mathcal{F},$$

(3)

that approximates the actual OFSM state-register set ${\mathcal{F}}_{\mathrm{OFSM}}$.

Register names containing OFSM-related information are retained in the experimental dataset only to construct ground-truth labels and evaluate localization accuracy. They are not included in the feature vector or provided to the classifier during training or prediction. Consequently, the localization decision is based exclusively on timing and switching-activity characteristics.

LOCATE therefore represents a localization attack rather than a complete deobfuscation attack. Correctly identifying the OFSM registers does not reveal their state encoding, transition relationships, secret key, or original FSM functionality. Nevertheless, localization can substantially reduce the portion of the sequential logic that must be considered during subsequent reverse-engineering or deobfuscation analysis.

The adversary is assumed to know the FSM-obfuscation methodology used to protect the target circuit but does not know which flip-flops in the target implementation belong to the OFSM. To construct labeled training data, the adversary can apply the known ProtectIP obfuscation flow [4] to attacker-controlled or publicly available circuits. Because the adversary generates these labeled training designs, the corresponding OFSM-register identities are known during model construction.

The trained localization model is then applied to a different, previously unseen ProtectIP-obfuscated target circuit. No OFSM labels from the target design are used during training or prediction. The attack therefore evaluates whether implementation-level fingerprints learned from independently obfuscated training designs transfer to an unseen protected implementation.

Table 1. Summary of the LOCATE Threat Model.

Threat-Model Element	Assumption
Protection knowledge	The adversary knows that the target is protected using the ProtectIP state-space obfuscation methodology.
Training capability	The adversary can generate independently obfuscated, labeled training designs using the known ProtectIP flow.
Target design	The target circuit is previously unseen and is excluded completely from model training.
Available observables	Per-register setup timing, hold timing, and switching activity are available from the implementation-analysis environment.
Target OFSM labels	No OFSM-register labels from the target circuit are available during training or prediction.
Register identifiers	Register names and designer annotations are not used by the localization model.
Structural information	Explicit fan-in/fan-out connectivity, feedback paths, logic-cone characteristics, and state-transition relationships are not used.
Attack objective	The objective is to localize candidate OFSM state registers within the complete register population.
Out of scope	LOCATE does not recover the original state-transition graph, state encoding, secret key, or complete circuit functionality.

Table 1. Summary of the LOCATE Threat Model.

Threat-Model Element	Assumption
Protection knowledge	The adversary knows that the target is protected using the ProtectIP state-space obfuscation methodology.
Training capability	The adversary can generate independently obfuscated, labeled training designs using the known ProtectIP flow.
Target design	The target circuit is previously unseen and is excluded completely from model training.
Available observables	Per-register setup timing, hold timing, and switching activity are available from the implementation-analysis environment.
Target OFSM labels	No OFSM-register labels from the target circuit are available during training or prediction.
Register identifiers	Register names and designer annotations are not used by the localization model.
Structural information	Explicit fan-in/fan-out connectivity, feedback paths, logic-cone characteristics, and state-transition relationships are not used.
Attack objective	The objective is to localize candidate OFSM state registers within the complete register population.
Out of scope	LOCATE does not recover the original state-transition graph, state encoding, secret key, or complete circuit functionality.

Under this threat model, the central security question is whether ProtectIP-obfuscated FSM implementations leave sufficiently distinguishable timing and switching-activity fingerprints to enable their state registers to be localized without explicit structural analysis of the target FSM.

3.1. Practical Attack Workflow

Under the considered threat model, the adversary first constructs labeled training data using the known ProtectIP obfuscation methodology. Publicly available or attacker-controlled FSM circuits are obfuscated independently using the same ProtectIP flow and subsequently processed through the synthesis and implementation-analysis environment. Because these training designs are generated by the adversary, the corresponding OFSM-register identities are known and can be used as ground-truth labels during model construction.

For each register in the training designs, LOCATE extracts the three implementation-level observables considered in this work: setup timing, hold timing, and switching activity. These measurements form the per-register feature vectors used to train the Random Forest localization model.

The trained model is then applied to a different, previously unseen ProtectIP-obfuscated target circuit. The same three features are extracted for every target flip-flop and supplied to the trained classifier, which assigns each register an OFSM or non-OFSM prediction. No OFSM labels from the target design are required during training or prediction. The resulting predicted OFSM set therefore provides a reduced collection of candidate state registers that can be prioritized during subsequent reverse-engineering or deobfuscation analysis.

4. Proposed OFSM Register Localization Methodology

4.1. Methodology Overview

LOCATE aims to localize the state registers associated with an obfuscated finite-state machine (OFSM) from the remaining sequential elements of a design. Each flip-flop is characterized using implementation-derived timing and switching-activity information. The underlying hypothesis is that OFSM state registers interact with a common next-state logic structure and may therefore exhibit implementation-level characteristics that differ statistically from other flip-flops in the design.

The localization process consists of four main stages: 1) extraction of register-level timing and switching-activity measurements, 2) construction and preprocessing of per-register feature vectors, 3) Random Forest-based OFSM register classification, and 4) evaluation under within-design and cross-design settings.

For every flip-flop $F{F}_i$, three features are considered:

$${\mathbf{x}}_i=[S_i,H_i,T_i],$$

(4)

where $S_i$ represents the setup-timing measurement, $H_i$ represents the hold-timing measurement, and $T_i$ represents the switching activity associated with $F{F}_i$. These three implementation-level measurements constitute the complete feature vector used by the localization model.

4.2. Timing and Switching-Activity Feature Extraction

The first stage constructs a numerical profile for every flip-flop in the analyzed design. Three implementation-level characteristics are extracted: setup timing, hold timing, and switching activity.

4.2.1. Setup Timing

The setup feature $S_i$ represents the setup-related timing measurement associated with flip-flop $F{F}_i$. This feature captures the timing behavior of the data path terminating at the register under setup analysis. Differences in the combinational logic feeding OFSM registers may therefore produce setup characteristics that differ from those of other registers in the design.

4.2.2. Hold Timing

The hold feature $H_i$ represents the corresponding hold-related timing measurement associated with $F{F}_i$. Whereas setup analysis characterizes the timing behavior of paths terminating at the register under the setup constraint, the hold feature provides complementary information about short-path timing behavior. The experimental analysis therefore examines whether the combination of setup and hold characteristics improves the separation of OFSM and non-OFSM registers.

4.2.3. Switching Activity

The switching feature $T_i$ represents the toggle activity associated with $F{F}_i$. Because state registers change according to the transitions of the protected state machine, their switching behavior is influenced by reachable states, transition conditions, and the surrounding next-state logic. Switching activity therefore provides a behavioral dimension that is complementary to the two timing features.

For a design containing N flip-flops, the resulting feature matrix is

$$\mathbf{X}=\left[\begin{array}{ccc}{S}_1& H_1& T_1\\ S_2& H_2& T_2\\ ⋮& ⋮& ⋮\\ S_N& H_N& T_N\end{array}\right].$$

(5)

Each row of $\mathbf{X}$ represents one flip-flop, while the three columns correspond to its setup-timing, hold-timing, and switching-activity measurements.

4.3. Data Preprocessing and Ground-Truth Construction

Before classification, invalid infinite timing values are treated as missing observations. Missing feature values are replaced using median imputation. To prevent information from the evaluation samples from influencing preprocessing, the median values are determined exclusively from the corresponding training data and are subsequently applied to the held-out samples.

For experimental evaluation, each flip-flop is assigned a binary ground-truth label

$$y_i=\left\{\begin{array}{cc}1,\hfill & F{F}_i\in {\mathcal{F}}_{\mathrm{OFSM}},\hfill \\ 0,\hfill & F{F}_i\notin {\mathcal{F}}_{\mathrm{OFSM}}.\hfill \end{array}\right.$$

(6)

The OFSM designation contained in the benchmark register identifiers is used only to construct the ground-truth labels required for experimental evaluation. The identifiers themselves are not included in the feature vector. Consequently, the localization model operates exclusively on the three numerical features $S_i$, $H_i$, and $T_i$.

4.4. OFSM Register Classification

A Random Forest (RF) classifier [18] is employed to learn the distinction between OFSM and non-OFSM registers. Random Forest is suitable for this analysis because the relationship among setup timing, hold timing, and switching activity is not assumed to be linear. The classifier can therefore model nonlinear decision boundaries and interactions among the three features without requiring manually selected thresholds for the individual measurements.

The classifier consists of 300 decision trees. To account for the imbalance between the relatively small number of OFSM registers and the larger population of non-OFSM flip-flops, balanced class weighting is used during training. The random seed is fixed to 42 for reproducibility, and the minimum number of samples required at a leaf node is set to one.

For a flip-flop represented by the feature vector ${\mathbf{x}}_i$, the trained classifier produces the binary prediction

$${\widehat{y}}_i=f\left({\mathbf{x}}_i\right),$$

(7)

where ${\widehat{y}}_i=1$ indicates that the flip-flop is predicted to belong to the OFSM and ${\widehat{y}}_i=0$ indicates that it is predicted to be a non-OFSM register.

The resulting predictions provide a localized set of candidate OFSM state registers. The classifier does not reconstruct the state-transition graph, determine the state encoding, or recover the functionality of the protected FSM.

4.5. Cross-Validation and Evaluation Procedure

Two complementary evaluation procedures are used to characterize LOCATE.

First, a within-design stratified five-fold cross-validation experiment is performed to determine whether OFSM and non-OFSM registers are separable within the same implementation. For each benchmark, the flip-flops are divided into five folds while preserving approximately the same OFSM-to-non-OFSM ratio. Four folds are used for training and the remaining fold is used for testing. The procedure is repeated until every flip-flop has been evaluated once. This experiment characterizes the intrinsic separability of the timing and switching-activity fingerprints within each individual design.

Second, cross-design generalization is evaluated using leave-one-design-out (LODO) validation. In each experiment, five benchmark circuits are pooled to construct the labeled training set, while the remaining circuit is treated as a completely unseen target design. The classifier is trained exclusively using registers from the five training designs and is subsequently applied to all flip-flops in the target circuit. No labeled registers from the target design are included during model training. The procedure is repeated six times such that each benchmark serves once as the unseen target.

Formally, for a set of benchmark designs

$$\mathcal{D}=\{D_1,D_2,\dots ,D_6\},$$

(8)

the training-design set associated with target design $D_k$ is

$${\mathcal{D}}_{\mathrm{train}}^{\left(k\right)}=\mathcal{D}\setminus \left\{D_k\right\},$$

(9)

while the complete register population of $D_k$ forms the corresponding test set. Thus, every prediction for $D_k$ is generated using a model trained without labeled examples from that design.

The same three features—setup timing, hold timing, and switching activity—are used in both evaluation settings. Infinite timing values are treated as missing observations, and median imputation is performed using parameters learned exclusively from the corresponding training data. The Random Forest configuration is maintained across all experiments, using 300 trees, balanced class weighting, a fixed random seed of 42, and a minimum leaf size of one.

For both evaluation procedures, predictions are summarized using true positives (TP), false positives (FP), and false negatives (FN). A true positive represents an OFSM register correctly localized by the classifier, a false positive represents a non-OFSM register incorrectly classified as OFSM, and a false negative represents an OFSM register missed by the classifier.

Precision is calculated as

$$\mathrm{Precision}={\displaystyle \frac{\mathrm{TP}}{\mathrm{TP}+\mathrm{FP}}},$$

(10)

to actual OFSM state registers. Recall is calculated as

$$\mathrm{Recall}={\displaystyle \frac{\mathrm{TP}}{\mathrm{TP}+\mathrm{FN}}},$$

(11)

and measures the proportion of actual OFSM registers successfully localized. The F1 score combines precision and recall as

$$\mathrm{F}1=2{\displaystyle \frac{\mathrm{Precision}\times \mathrm{Recall}}{\mathrm{Precision}+\mathrm{Recall}}}.$$

(12)

For the overall result, TP, FP, and FN counts are first aggregated across the six evaluated designs, after which precision, recall, and F1 score are calculated from the combined counts. This micro-aggregation accounts for differences in the number of OFSM registers among the benchmark circuits.

Together, the within-design and cross-design evaluations distinguish between two aspects of the proposed approach. The within-design experiment measures whether the implementation-level features provide sufficient separability within an individual circuit, whereas the LODO experiment evaluates whether the learned timing and switching-activity fingerprints transfer to a previously unseen protected design.

5. Experimental Setup and Results

5.1. Experimental Setup and Benchmarks

The benchmark circuits were obfuscated using the ProtectIP state-space obfuscation methodology proposed by Rahman and Bhunia [4]. ProtectIP modifies the state space and associated transition behavior of the original finite-state machine to hinder reverse engineering of the protected control logic. The resulting protected state registers are referred to as OFSM registers throughout this work. For consistency across benchmarks, the same default ProtectIP configuration and obfuscation flow were applied to all evaluated circuits.

LOCATE was evaluated using six circuits from the ISCAS’89 sequential benchmark suite  [19]: s5378, s13207, s15850, s35932, s38417, and s38584. The evaluated designs vary substantially in size and in the proportion of registers associated with the obfuscated FSM, providing different circuit configurations and levels of class imbalance for evaluation.

For each benchmark, register-level setup timing, hold timing, and switching activity were extracted to construct the feature vectors described in Section 4. Ground-truth OFSM designations were retained for experimental evaluation but were not included in the numerical feature vectors used by the localization model.

Table 2 summarizes the evaluated benchmarks. The six circuits contain a total of 4,743 flip-flops, of which 331 correspond to OFSM state registers. The number of OFSM registers ranges from 19 in s5378 to 89 in s38417, while the total number of flip-flops varies from 198 to 1,653. These differences provide varying OFSM populations and class-imbalance conditions across the evaluated designs.

5.2. Synthesis, Timing, and Activity Analysis Environment

To ensure a consistent experimental environment, all benchmark circuits were processed using the same synthesis and analysis flow. Each design was synthesized and technology mapped using Synopsys Design Compiler (DC Shell) with the LEDA 250-nm standard-cell library (lec25dscc25.db). A clock period of 5 ns was applied consistently to all evaluated designs.

Following synthesis and technology mapping, DC Shell was used to generate timing and switching-activity reports for the mapped designs. For each flip-flop, setup- and hold-related timing measurements were extracted from the corresponding timing reports. Switching activity was obtained using vectorless activity estimation, from which the reported toggle activity associated with each flip-flop was extracted. The same analysis procedure, standard-cell library, and timing constraints were used for all benchmark circuits.

These measurements provide the three implementation-level features used by LOCATE: setup timing, hold timing, and switching activity. The resulting per-register data were processed using the preprocessing and classification procedure described in Section 4.

The same Random Forest configuration and preprocessing procedure were maintained across all experiments. For the within-design evaluation, training and testing were performed separately within each benchmark using stratified five-fold cross-validation. For the cross-design LODO evaluation, registers from five benchmark circuits were pooled to form the training set, while the remaining circuit was treated as the unseen target. This consistent implementation environment allows the evaluation to focus on transferability across circuit designs while holding the synthesis flow, technology library, timing constraint, and feature-extraction procedure fixed.

Table 3. Implementation and Evaluation Configuration.

Parameter	Configuration
Synthesis / analysis tool	Synopsys Design Compiler (DC Shell)
Technology library	lec25dscc25.db
Clock period	5 ns
Obfuscation method	ProtectIP state-space obfuscation
Obfuscation configuration	Same default ProtectIP configuration for all benchmarks
Register-level features	Setup timing, hold timing, switching activity
Activity estimation	Vectorless switching-activity estimation
Classifier	Random Forest
Number of trees	300
Class weighting	Balanced
Minimum leaf size	1
Random seed	42
Missing-value handling	Median imputation using training data only
Within-design evaluation	Stratified five-fold cross-validation
Cross-design evaluation	Leave-one-design-out (LODO)
Target labels in LODO	Not used during training or prediction

Table 3. Implementation and Evaluation Configuration.

Parameter	Configuration
Synthesis / analysis tool	Synopsys Design Compiler (DC Shell)
Technology library	lec25dscc25.db
Clock period	5 ns
Obfuscation method	ProtectIP state-space obfuscation
Obfuscation configuration	Same default ProtectIP configuration for all benchmarks
Register-level features	Setup timing, hold timing, switching activity
Activity estimation	Vectorless switching-activity estimation
Classifier	Random Forest
Number of trees	300
Class weighting	Balanced
Minimum leaf size	1
Random seed	42
Missing-value handling	Median imputation using training data only
Within-design evaluation	Stratified five-fold cross-validation
Cross-design evaluation	Leave-one-design-out (LODO)
Target labels in LODO	Not used during training or prediction

5.3. Timing and Switching-Activity Characteristics

Before evaluating the classifier, we examine whether OFSM state registers exhibit measurable differences from the remaining flip-flops in each design. For every benchmark, the mean setup timing, hold timing, and switching activity were calculated separately for OFSM and non-OFSM registers. Table 4 summarizes the resulting measurements.

OFSM registers exhibit lower mean setup values than non-OFSM registers in every evaluated design. For example, in s38584, the mean setup value decreases from 2.787 for non-OFSM registers to 0.824 for OFSM registers. Similarly, s38417 exhibits a decrease from 2.742 to 0.996. The same direction of separation is observed across the remaining benchmarks.

The opposite trend is observed for hold timing. OFSM registers consistently exhibit higher mean hold values than the non-OFSM population. In s35932, for example, the mean hold value increases from 0.265 for non-OFSM registers to 0.634 for OFSM registers. Similar differences are observed across the other evaluated designs.

Switching activity provides an additional behavioral characteristic. Across all six benchmarks, the mean toggle activity of OFSM registers is higher than that of the corresponding non-OFSM population. The magnitude of this difference, however, varies substantially across designs. For example, s35932 exhibits mean toggle activities of approximately 0.00002 and 0.05131 for non-OFSM and OFSM registers, respectively, whereas the corresponding values for s5378 are 0.04885 and 0.05967.

Taken together, the measurements reveal a recurring implementation-level signature. Relative to the non-OFSM register population, OFSM state registers tend to exhibit

$$S_{\mathrm{OFSM}}<S_{\mathrm{Non}-\mathrm{OFSM}},$$

(13)

$$H_{\mathrm{OFSM}}>H_{\mathrm{Non}-\mathrm{OFSM}},$$

(14)

and, on average,

$$T_{\mathrm{OFSM}}>T_{\mathrm{Non}-\mathrm{OFSM}}.$$

(15)

These relationships represent statistical tendencies rather than deterministic classification rules. Individual OFSM and non-OFSM registers occupy overlapping regions of the feature space, motivating the use of multiple complementary features rather than a single threshold.

As illustrated in Figure 4, OFSM registers tend to occupy regions characterized by lower setup and higher hold values, while the non-OFSM population is concentrated more strongly toward higher setup and lower hold values. The overlap between the two populations also explains why localization performance varies across individual circuits.

5.4. Within-Design OFSM Register Localization

We first evaluate whether the proposed timing and switching-activity features provide sufficient information to separate OFSM and non-OFSM registers within the same implementation. This experiment uses the per-design stratified five-fold cross-validation procedure described in Section 4.5. The purpose of this evaluation is to characterize the intrinsic separability of the proposed implementation-level feature set when training examples from the same circuit are available.

Table 5 presents the resulting within-design localization performance. For each benchmark, the table reports the number of actual OFSM registers, correctly localized OFSM registers, missed OFSM registers, false positives, precision, recall, and F1 score.

Across the six benchmarks, 281 of the 331 OFSM state registers are correctly localized while producing 14 false positives. Micro-aggregation across all designs yields an overall precision of 95.3%, recall of 84.9%, and F1 score of 89.8%. These results demonstrate substantial within-design separability between OFSM and non-OFSM registers using the proposed feature set.

The per-design results show that the strength of this separability varies across circuit implementations. For s35932, all 84 OFSM registers are correctly localized without a false positive, resulting in 100% precision, recall, and F1 score. The s5378 benchmark also exhibits strong separability, achieving 100% precision and 89.5% recall. The larger s38417 and s38584 designs achieve F1 scores of 91.0% and 86.4%, respectively.

The more challenging cases are s13207 and s15850, which achieve F1 scores of 77.8% and 75.9%, respectively. Their lower recall indicates greater overlap between the OFSM and non-OFSM register populations in the considered feature space. Nevertheless, precision remains above 84% for both designs, indicating that most registers selected as OFSM candidates correspond to actual OFSM state registers.

Although the within-design results establish strong feature separability, this evaluation allows training examples from the same circuit as the test samples. A cross-design evaluation is therefore performed next to determine whether the learned fingerprint transfers to a previously unseen target circuit.

To evaluate transferability across circuit boundaries, we perform the leave-one-design-out (LODO) evaluation described in Section 4.5. In each experiment, five ProtectIP-obfuscated benchmark circuits form the labeled training set, while the remaining circuit is treated as a previously unseen target design.

The classifier is trained exclusively using labeled registers from the five training designs and is subsequently applied to all flip-flops in the target circuit. No labeled examples from the target design are included during model construction. Successful localization therefore requires the classifier to learn implementation-level characteristics that transfer across independently obfuscated circuits.

Table 6 summarizes the resulting cross-design localization performance. Across the six unseen-target experiments, the classifier correctly localizes 266 of the 331 OFSM state registers while producing 39 false positives. Micro-aggregation across all six target designs yields an overall precision of 87.2%, recall of 80.4%, and F1 score of 83.6%.

The cross-design evaluation shows that the OFSM fingerprint is not restricted to circuits represented during training. When each target design is excluded completely from its corresponding training set, the classifier retains an aggregate F1 score of 83.6%. Relative to the within-design evaluation, precision decreases from 95.3% to 87.2%, recall from 84.9% to 80.4%, and F1 score from 89.8% to 83.6%. These reductions correspond to 8.1, 4.5, and 6.2 percentage points, respectively.

Performance varies across the individual target designs. For s35932, 71 of the 84 OFSM registers are localized without a false positive, resulting in 100% precision, 84.5% recall, and an F1 score of 91.6%. The s5378, s38417, and s38584 targets achieve F1 scores of 85.0%, 83.8%, and 85.1%, respectively.

The lowest cross-design performance occurs for s15850. When s15850 is excluded from training, 18 of its 32 OFSM registers are localized, corresponding to 75.0% precision, 56.3% recall, and an F1 score of 64.3%. This result indicates greater overlap between the implementation characteristics of OFSM and non-OFSM registers in this target relative to the characteristics learned from the remaining five designs.

From the attack perspective, the aggregate results show that a model trained entirely on other ProtectIP-obfuscated circuits can recover approximately 80% of the OFSM registers in previously unseen target implementations while maintaining precision above 87%. Thus, labeled training circuits generated using the known obfuscation methodology can provide sufficient information to produce a substantially reduced set of candidate OFSM state registers in an unseen protected circuit.

Despite the more restrictive cross-design setting, the classifier retains an F1 score of 83.6%, providing evidence that a substantial portion of the measured implementation-level fingerprint transfers across circuit designs.

As shown in Figure 2, the cross-design evaluation results in a moderate reduction in precision, recall, and F1 score relative to within-design validation while retaining useful localization performance on unseen target circuits.

Figure 2. Comparison of within-design and cross-design OFSM register localization performance. Cross-design leave-one-design-out (LODO) evaluation results in a moderate reduction in precision, recall, and F1 score relative to within-design validation, while maintaining strong overall performance on previously unseen target circuits.

Figure 2. Comparison of within-design and cross-design OFSM register localization performance. Cross-design leave-one-design-out (LODO) evaluation results in a moderate reduction in precision, recall, and F1 score relative to within-design validation, while maintaining strong overall performance on previously unseen target circuits.

5.5. Feature Ablation Analysis

To quantify the contribution of each observable characteristic, an ablation study was performed using the individual features and different feature combinations. The same preprocessing, Random Forest configuration, and within-design cross-validation procedure were maintained for all feature configurations. Table 7 summarizes the aggregated results across the six benchmark circuits.

5.6. Effect of Feature Normalization

Because the magnitudes of timing and switching-activity measurements can vary across circuit designs, we additionally evaluated whether feature normalization improves cross-design generalization. Three representations were considered: the original raw features, robust normalization based on the training-set median and interquartile range, and rank-based normalization.

The raw feature representation achieved the highest cross-design performance, with an aggregate F1 score of 83.6%. Robust normalization reduced the F1 score to 81.0%, while rank normalization further reduced it to 75.8%. These results indicate that the absolute magnitudes of the implementation-level measurements contain useful information for OFSM register localization. Consequently, the raw setup-timing, hold-timing, and switching-activity measurements are used in the primary experiments.

Among the individual features, setup timing provides the strongest discriminative capability, achieving an F1 score of 67.2%. Hold timing alone achieves an F1 score of 56.4%, while switching activity alone achieves 47.8%. These results indicate that no individual feature provides the localization performance obtained by combining multiple implementation-level characteristics.

Combining setup and hold timing substantially improves localization performance. The two timing features correctly localize 270 OFSM registers while producing 29 false positives, corresponding to 90.3% precision, 81.6% recall, and an F1 score of 85.7%. This improvement indicates that setup and hold measurements provide complementary information about the timing behavior associated with OFSM state registers.

Adding switching activity provides a further improvement. The complete three-feature configuration increases the number of correctly localized OFSM registers from 270 to 281 while reducing false positives from 29 to 14. Consequently, precision increases from 90.3% to 95.3%, recall from 81.6% to 84.9%, and F1 score from 85.7% to 89.8%.

Although switching activity is the weakest feature when considered independently, its inclusion improves all three performance metrics when combined with setup and hold timing. This result indicates that switching activity provides complementary information for registers that are not reliably separated using timing characteristics alone.

As shown in Figure 3, the largest improvement is obtained by combining the two timing features, while adding switching activity provides a further increase in localization performance.

6. Discussion and Limitations

The experimental results show that OFSM state registers exhibit measurable implementation-level characteristics in their timing and switching activity. The within-design evaluation achieves 95.3% precision, 84.9% recall, and an F1 score of 89.8%, demonstrating strong separability within the evaluated implementations. More importantly, the cross-design leave-one-design-out (LODO) evaluation achieves 87.2% precision, 80.4% recall, and an F1 score of 83.6% when the target circuit is completely excluded from training. Together, these results indicate that a substantial portion of the observed implementation-level fingerprint transfers across independently obfuscated designs.

6.1. Security Implications

The cross-design results are particularly relevant from an adversarial perspective because the localization model does not require labeled examples from the target implementation. Under the LODO evaluation, the model is trained using independently generated ProtectIP-obfuscated training designs and is subsequently applied to a previously unseen target circuit. The resulting 87.2% precision, 80.4% recall, and 83.6% F1 score indicate that the timing and switching-activity characteristics learned from other protected circuits remain useful for localizing OFSM registers in an unseen implementation.

An adversary who knows the protection methodology can therefore construct labeled training examples by applying the same obfuscation flow to other available circuits. The resulting model can then be used to reduce the set of sequential elements that require further analysis in a protected target. The primary security implication is that concealing the logical behavior of an FSM does not necessarily eliminate implementation-level characteristics associated with its protected state registers.

This localization capability does not constitute complete deobfuscation. The proposed method does not recover the original state-transition graph, state encoding, secret key, or functional behavior of the protected FSM. Nevertheless, reducing the complete register population to a smaller set of candidate OFSM registers can provide a useful starting point for subsequent reverse-engineering or deobfuscation analysis.

Under the cross-design evaluation, 266 true OFSM registers are localized together with 39 false positives, producing a total of 305 candidate registers across the six unseen-target experiments. Of these candidates, 87.2% correspond to actual OFSM registers, while 80.4% of all OFSM registers are recovered. These results show that the proposed attack can produce a substantially concentrated candidate set without requiring labeled registers from the target circuit.

The feature-ablation results provide additional insight into the source of this distinguishability. In the within-design evaluation, setup timing is the strongest individual feature, achieving an F1 score of 67.2%. Combining setup and hold timing increases the F1 score to 85.7%, while adding switching activity further increases it to 89.8%. Thus, the observed fingerprint is not attributable to a single measurement. Instead, setup timing, hold timing, and switching activity provide complementary information that jointly improves OFSM register localization.

6.2. Reduction of the Candidate Register Space

From an adversarial perspective, localization is useful when it substantially reduces the number of registers that must be considered during subsequent reverse-engineering analysis. Across the six leave-one-design-out experiments, LOCATE identifies 305 candidate registers, consisting of 266 true OFSM registers and 39 false positives, from a total population of 4,743 flip-flops.

Thus, the localization stage reduces the candidate register population to approximately 6.4% of the original sequential elements, corresponding to a reduction of approximately 93.6% in the register search space. At the same time, 80.4% of the actual OFSM registers are retained in the localized candidate set. These results illustrate the practical value of localization as a preprocessing stage for subsequent FSM-recovery or deobfuscation analysis.

The practical impact of localization errors depends on whether a register is falsely included in or excluded from the candidate set. A false positive introduces an additional non-OFSM register that must be examined during subsequent analysis, increasing the downstream reverse-engineering effort but not directly preventing further investigation. In contrast, a false negative corresponds to an actual OFSM state register that is absent from the localized candidate set and may therefore hinder subsequent attempts to reconstruct the protected state machine.

Under the cross-design evaluation, LOCATE produces 39 false positives while missing 65 of the 331 OFSM registers. Although the localization stage does not recover every OFSM register, the resulting candidate set retains 80.4% of the protected registers while reducing the overall register population substantially. These results indicate that LOCATE is most naturally used as a preprocessing step that prioritizes a smaller subset of registers for more detailed structural or functional analysis rather than as a standalone complete deobfuscation method.

6.3. Variation Across Designs

Localization performance varies across the evaluated benchmark circuits, indicating that the strength of the observed implementation-level fingerprint depends on the particular design. This variation is visible in both the within-design and cross-design evaluations.

Under within-design validation, s35932 exhibits complete separability: all 84 OFSM registers are correctly localized without a false positive, resulting in 100% precision, recall, and F1 score. In contrast, s13207 and s15850 achieve lower recall values of 71.8% and 68.8%, respectively. These results indicate greater overlap between the OFSM and non-OFSM register populations in those implementations.

A similar variation is observed under the more restrictive cross-design LODO evaluation. The strongest result again occurs for s35932, which achieves 100% precision, 84.5% recall, and an F1 score of 91.6%. The most challenging target is s15850, which achieves 75.0% precision, 56.3% recall, and an F1 score of 64.3% when completely excluded from training.

Such differences are expected because the timing and switching characteristics of a register depend on the surrounding combinational logic, circuit topology, synthesis optimization, and the resulting mapped implementation. In some designs, OFSM registers form a relatively distinct population in the considered feature space, whereas in others their characteristics overlap more strongly with those of non-OFSM registers.

LOCATE should therefore be interpreted as a statistical localization method rather than a deterministic rule that guarantees recovery of every OFSM state register. The design-dependent variation observed in the experiments also motivates broader evaluation across additional circuits, synthesis conditions, and technology libraries.

Figure 4. Distribution of setup- and hold-timing measurements for OFSM and non-OFSM registers across the six evaluated benchmark designs. OFSM registers tend to exhibit lower setup values and higher hold values than non-OFSM registers, although the two populations overlap in parts of the feature space.

Figure 4. Distribution of setup- and hold-timing measurements for OFSM and non-OFSM registers across the six evaluated benchmark designs. OFSM registers tend to exhibit lower setup values and higher hold values than non-OFSM registers, although the two populations overlap in parts of the feature space.

6.4. Limitations

The proposed analysis has several limitations that define the scope of the current results.

First, the presented technique performs OFSM register localization rather than complete FSM recovery. Identifying candidate state registers does not reveal their state encoding, relationships among state bits, state-transition graph, secret key, or the original functionality of the protected FSM. Additional analysis would therefore be required to transform the localized register set into a complete deobfuscation attack.

Second, although the leave-one-design-out evaluation demonstrates cross-design transferability, all evaluated circuits were processed using the same standard-cell library, timing constraint, synthesis flow, and ProtectIP-based obfuscation methodology. The current results therefore demonstrate generalization across circuit designs under a fixed implementation environment, but do not establish transferability across technology libraries, synthesis configurations, timing constraints, operating conditions, or different FSM-obfuscation mechanisms.

Third, LOCATE assumes access to the register-level timing and switching-activity information defined in the threat model. The results should therefore be interpreted under an implementation-analysis adversary capable of obtaining such measurements, rather than as a purely external physical side-channel attack.

Fourth, the experimental evaluation is limited to six ISCAS’89 benchmark circuits and a single ProtectIP-based implementation flow. Changes in circuit structure, synthesis optimization, activity estimation, technology mapping, or obfuscation configuration may alter the resulting feature distributions. Evaluation across additional benchmark suites, technology libraries, synthesis conditions, and obfuscation configurations is therefore needed to determine the broader robustness of the observed fingerprints.

Finally, LOCATE currently relies on supervised learning and requires labeled OFSM examples during model construction. In the cross-design attack setting, these labels are obtained from independently generated training designs rather than from the target circuit. Investigating unsupervised, semi-supervised, or transfer-learning approaches that reduce the dependence on labeled training data represents an important direction for future work.

Despite these limitations, the results show that ProtectIP-obfuscated FSM implementations can expose measurable register-level timing and switching-activity characteristics that remain useful for localization across previously unseen circuit designs. These findings motivate further investigation of implementation-level leakage when evaluating FSM-obfuscation techniques.

7. Conclusion

This work investigated whether obfuscated finite-state machine (OFSM) state registers can be localized using implementation-level timing and switching-activity information. LOCATE characterizes each flip-flop using three numerical features—setup timing, hold timing, and switching activity—and applies a supervised Random Forest model to distinguish OFSM from non-OFSM registers.

The approach was evaluated on six ProtectIP-obfuscated ISCAS’89 benchmark circuits containing 4,743 flip-flops, including 331 OFSM state registers. Under within-design five-fold validation, 281 of the 331 OFSM registers were correctly localized with 14 false positives, yielding 95.3% precision, 84.9% recall, and an F1 score of 89.8%. More importantly, leave-one-design-out cross-design evaluation achieved 87.2% precision, 80.4% recall, and an F1 score of 83.6% when the target circuit was completely excluded from training. These results indicate that a substantial portion of the observed implementation-level fingerprint transfers across independently obfuscated circuit designs.

Feature-ablation analysis further showed that setup timing provides the strongest individual discrimination, while combining setup and hold timing substantially improves localization performance. Switching activity is weaker when considered independently but provides complementary information that further improves the combined feature set.

The results demonstrate that ProtectIP-obfuscated FSM implementations can expose measurable timing and switching-activity characteristics that support localization of protected state registers. Although the proposed approach does not recover the state-transition graph, state encoding, secret key, or original FSM functionality, it can reduce the set of candidate registers that must be considered during subsequent reverse-engineering or deobfuscation analysis.

Future work will investigate the robustness of these fingerprints across different technology libraries, synthesis configurations, timing constraints, operating conditions, and FSM-obfuscation mechanisms. Additional directions include evaluation across broader benchmark suites and the development of unsupervised, semi-supervised, and transfer-learning approaches that reduce the dependence on labeled training designs.