Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

Experimental Evaluation of SAT Attack on Logic Locking

Version 1 : Received: 7 March 2024 / Approved: 7 March 2024 / Online: 7 March 2024 (11:17:33 CET)

How to cite: Vojvoda, M.; Hromada, V.; Janikovský, F.; Kučerák, J.; Jókay, M. Experimental Evaluation of SAT Attack on Logic Locking. Preprints 2024, 2024030447. https://doi.org/10.20944/preprints202403.0447.v1 Vojvoda, M.; Hromada, V.; Janikovský, F.; Kučerák, J.; Jókay, M. Experimental Evaluation of SAT Attack on Logic Locking. Preprints 2024, 2024030447. https://doi.org/10.20944/preprints202403.0447.v1

Abstract

To secure logic circuits against the illegal copying the insertion of the so-called key bit inputs using XOR/XNOR gates has been proposed in . The inserted gates modify (lock) the behavior of the original circuit and only the correct choice of the secret key bits guarantees the equivalent behaviour of the locked circuit to the original circuit. To break this kind of security, i.e. to find the secret key bits, there was a SAT solver based attack proposed in . The aim of this work is to experimentally verify this attack on several locked circuits with various number of primary inputs and outputs and with various number of gates. Except for the random placement of the key gates we evaluate also the positioning with chaining elimination. The obtained and presented results show that we were able to unlock 10 of 11 circuits within few minutes on a common PC.

Keywords

logic locking; piracy protection; SAT attack

Subject

Computer Science and Mathematics, Security Systems

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