Article
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Preserved in Portico This version is not peer-reviewed
Cross-Mesh Clock Network Synthesis
Version 1
: Received: 21 July 2023 / Approved: 21 July 2023 / Online: 25 July 2023 (10:19:40 CEST)
A peer-reviewed article of this Preprint also exists.
Cheng, W.-K.; Yeh, Z.-M.; Kao, H.-Y.; Huang, S.-H. Cross-Mesh Clock Network Synthesis. Electronics 2023, 12, 3410. Cheng, W.-K.; Yeh, Z.-M.; Kao, H.-Y.; Huang, S.-H. Cross-Mesh Clock Network Synthesis. Electronics 2023, 12, 3410.
Abstract
In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. To achieve this target, a hybrid clock network architecture that combines both clock tree and clock mesh seems to be a promising solution. In this paper, we propose a novel clock mesh architecture – cross-mesh, with the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating and register clustering techniques to further reduce dynamic power consumption. The proposed algorithms have four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our methodology and algorithms get feasible solution effectively and improve both power consumption and clock skew simultaneously.
Keywords
clock mesh; clock tree; clock skew; clock gating; register clustering
Subject
Engineering, Electrical and Electronic Engineering
Copyright: This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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