Preprint Article Version 1 Preserved in Portico This version is not peer-reviewed

A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design using an Approximate Multiplier

Version 1 : Received: 19 June 2023 / Approved: 20 June 2023 / Online: 21 June 2023 (03:49:43 CEST)

A peer-reviewed article of this Preprint also exists.

Shang, J.-J.; Phipps, N.; Wey, I.-C.; Teo, T.H. A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier. Chips 2023, 2, 159-172. Shang, J.-J.; Phipps, N.; Wey, I.-C.; Teo, T.H. A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier. Chips 2023, 2, 159-172.

Abstract

For Convolutional Neural Network (CNN), Depthwise Separable CNN (DSCNN) is a preferred architecture for Application Specific Integrated Circuit (ASIC) implementation on edge devices. It can benefit from a multi-mode approximate multiplier proposed in this work. The proposed approximate multiplier uses two 4-bit multiplication operations to implement a 12-bit multiplication operation by reusing the same multiplier array. With this approximate multiplier, sequential multiplication operations are pipelined in a modified DSCNN to fully utilize the PE array in the convolutional layer. This Approximate (A-DSCNN) was implemented on TSMC 40-nm CMOS process with a supply voltage of 0.9 V. At the clock frequency of 200 MHz, the design achieves 4.78 GOPs/mW while occupying 1.24 mm x 1.24 mm silicon area. Compared to conventional DSCNN implemented in a similar process node, the chip area and power consumption were reduced by 53% and 25%, while the throughput was improved by 17%.

Keywords

Application-Specific Integrated Circuits; Approximate Multiplier; CMOS; Convolutional Neural Network; Depthwise Separable Convolution; Processing Element

Subject

Engineering, Electrical and Electronic Engineering

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