Yttrium oxide (Y2O3) resistive random-access memory (RRAM) devices were fabricated using the sol–gel process on indium tin oxide/glass substrates. These devices exhibited conventional bipolar RRAM characteristics, without requiring a high voltage forming process. The effect of current compliance on the Y2O3 RRAM devices was investigated and revealed that as the set current compliance values increased, the resistance values gradually decreased. Consequently, intermediate resistance values were obtained, which are suitable for multi-level cell (MLC) switching. The fabricated Y2O3 RRAM devices were capable of functioning as an MLC with a capacity of 2 bits in one cell, utilizing three low resistance states and one common high resistance state. The potential of the Y2O3 RRAM for neural networks was further explored through numerical simulations. Hardware neural networks based on the Y2O3 RRAM demonstrated effective digit image classification with a high accuracy rate of approximately 88%, comparable to the ideal software-based classification (~92%). This suggests that the proposed RRAM has the potential to be utilized as a memory component in practical neuromorphic systems.

Recently, resistive random access memory (RRAM) has been an outstanding candidate among various emerging nonvolatile memories for high density storage and in-memory computing applications. However, the traditional RRAM, which accommodates two states depending on applied voltage, cannot meet the high density requirement in the era of big data. Many research groups have demonstrated that RRAM possesses the possibility of multi-level cell to overcome the demand of mass storage. Among numerous semiconductor materials, gallium oxide, as the fourth-generation semiconductor material, is highly-profile due to its excellent material proper-ties, and already be widely used in optoelectronics, high-power, resistive switching device and so on, due to its wide bandgap and transparent properties. In this study, we have successfully demonstrated the Al/GO/Ga2O3/ITO RRAM to achieve the possibility of two-bit storage. Compared to the single-layer counterpart, the bilayer structure has excellent electrical properties and stable reliability. The endurance characteristics could be enhanced above 100 switching cycles with an ON/OFF ratio of over 103. Moreover, the filament models are also described in this thesis to clarify the transport mechanisms.

Memristors were proposed in the early ’70s of the XXth century by Leon Chua as a new electrical element linking the charge and the flux. Since that first introduction, these devices have positioned themselves to be considered as possibly fundamental for the new generations of electronic devices. It has to be mentioned that actual memristors have only been recognized to exist as physical elements. In this paper, we apply a modeling framework to generate a model describing experimental measurements performed on a ReRAM. We show how to apply the Dynamic Route Map technique in the general case to obtain an approximation to the differential equation that determines the behaviour of the device.

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e. on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this work, we review the challenges involved and present a pathway to realize ultra-low-power mixed-signal NeuSoC, from device arrays and circuits to spike-based deep learning algorithms, with ‘brain-like’ energy-efficiency.