Kieu-Do-Nguyen, B.; The Binh, N.; Pham-Quoc, C.; Huynh, P. N.; Tran, N.-T.; Hoang, T.-T.; Pham, C.-K. Compact and Low-latency FPGA-based NTT Architecture for CRYSTALS Kyber Post-Quantum Cryptography Scheme. Preprints2024, 2024051452. https://doi.org/10.20944/preprints202405.1452.v1
APA Style
Kieu-Do-Nguyen, B., The Binh, N., Pham-Quoc, C., Huynh, P. N., Tran, N. T., Hoang, T. T., & Pham, C. K. (2024). Compact and Low-latency FPGA-based NTT Architecture for CRYSTALS Kyber Post-Quantum Cryptography Scheme. Preprints. https://doi.org/10.20944/preprints202405.1452.v1
Chicago/Turabian Style
Kieu-Do-Nguyen, B., Trong-Thuc Hoang and Cong-Kha Pham. 2024 "Compact and Low-latency FPGA-based NTT Architecture for CRYSTALS Kyber Post-Quantum Cryptography Scheme" Preprints. https://doi.org/10.20944/preprints202405.1452.v1
Abstract
In the era of the post-quantum Internet of Things (IoT), the implementation of anti-quantum cryptographic algorithms in numerous terminals can successfully defend against prospective quantum computing assaults. Lattice-based cryptography can withstand quantum computing attacks, making it a viable substitute for the currently prevalent classical public-key cryptographic technique. Nevertheless, the algorithm’s significant time complexity will result in a substantial computational burden on the edge computing chip in the IoT terminal. The computation of polynomial multiplication is the most demanding task in lattice-based cryptographic algorithms. Therefore, the investigation into efficient methods for calculating polynomial multiplication is highly important. Quick number theory transformations (NTT) are a widely employed technique to accelerate polynomial multiplication. This study presents a hardware implementation of an efficient number theory transformation. We utilize a multi-level pipeline architecture in the design to accomplish parallel calculations and execute it on a low-profile Artix7-XC7A100T FPGA device. The performance evaluation results demonstrate that our implementation significantly enhances performance and reduces resource usage compared to other existing proposals on the same platform. We suggested NTT core can be implemented in edge computing chips to enhance computational speed due to its small and low-latency design. The experimental results show that the proposed design, which supports both NTT and inverse NTT, achieves 417-Megahertz and consumes only 541-LUTs on Artix-7 XC7A100T.
Computer Science and Mathematics, Hardware and Architecture
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
,
