Version 1
: Received: 1 January 2024 / Approved: 3 January 2024 / Online: 3 January 2024 (07:48:08 CET)
How to cite:
Olakunle, N.O.; Hazzazi, F.; Chavda, C.; Veronis, G. Ternary Logic Gates Design in the Hybrid Memristor-TMD and Graphene FET. Preprints2024, 2024010142. https://doi.org/10.20944/preprints202401.0142.v1
Olakunle, N.O.; Hazzazi, F.; Chavda, C.; Veronis, G. Ternary Logic Gates Design in the Hybrid Memristor-TMD and Graphene FET. Preprints 2024, 2024010142. https://doi.org/10.20944/preprints202401.0142.v1
Olakunle, N.O.; Hazzazi, F.; Chavda, C.; Veronis, G. Ternary Logic Gates Design in the Hybrid Memristor-TMD and Graphene FET. Preprints2024, 2024010142. https://doi.org/10.20944/preprints202401.0142.v1
APA Style
Olakunle, N.O., Hazzazi, F., Chavda, C., & Veronis, G. (2024). Ternary Logic Gates Design in the Hybrid Memristor-TMD and Graphene FET. Preprints. https://doi.org/10.20944/preprints202401.0142.v1
Chicago/Turabian Style
Olakunle, N.O., Chintan Chavda and Georgios Veronis. 2024 "Ternary Logic Gates Design in the Hybrid Memristor-TMD and Graphene FET" Preprints. https://doi.org/10.20944/preprints202401.0142.v1
Abstract
Multiple valued logic (MVL) has proven to be a better alternative and solution to the challenges of traditional binary logic because of its fast computation, fewer interconnects, and small die. It is a potential candidate for future digital design because it allows energy-efficient, low-complex, and high-speed circuits. This paper introduces a new resistive-load two-dimensional field effect transistor-based ternary logic gates, wherein the active resistive-load is replaced with memristor to reduce chip area and power consumption. A memristor-based standard ternary inverter (STI) is designed using GNRFET, MoS2 FET, WSe2 FET, and FinFET, and their performance metric such as delay, power, and energy delay product (EDP) are analyzed. The results show that the proposed design achieves 50% reduction in circuit area, the average power dissipation is reduced by 11.7X, 6.8X, and 3.2X for GNRFET, MoS2 FET, and WSe2 FET, respectively, as compared to FinFET-based ternary inverter. Moreso, other logic gates such as OR, NOR, AND and NAND were simulated in T-SPICE EDA tool, and the results and truth table are in good agreement.
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
