Yamane, S.; Kriyama, T.; Wu, Y. An Efficient Reduction of Timer Interrupts for Model Checking of Embedded Assembly Programs. Electronics2024, 13, 463.
Yamane, S.; Kriyama, T.; Wu, Y. An Efficient Reduction of Timer Interrupts for Model Checking of Embedded Assembly Programs. Electronics 2024, 13, 463.
Yamane, S.; Kriyama, T.; Wu, Y. An Efficient Reduction of Timer Interrupts for Model Checking of Embedded Assembly Programs. Electronics2024, 13, 463.
Yamane, S.; Kriyama, T.; Wu, Y. An Efficient Reduction of Timer Interrupts for Model Checking of Embedded Assembly Programs. Electronics 2024, 13, 463.
Abstract
In verifying programs for embedded systems,
it is essential to reduce the verification time
because state explosion may occur in model checking.
One solution is to reduce the number of interrupt handler execution.
In particular, when periodic interrupts such as timer interrupts are incorporated, it is necessary to know the physical time.
In this paper, we define a control flow automata (CFA) that can handle time
and propose an algorithm based on interrupt handler execution reduction (IHER).
The proposed method reduces the number of interrupt executions,
including timer interrupts.
A case study verifies the effectiveness of this algorithm.
Keywords
model checking; embedded assembly program; reduction of interrupt handler executions
Subject
Computer Science and Mathematics, Software
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
