ARTICLE | doi:10.20944/preprints202107.0674.v1
Subject: Engineering, Automotive Engineering Keywords: Petri nets; programmable logic controllers; process modelling; digital twin
Online: 30 July 2021 (09:03:34 CEST)
Industrial discrete event dynamic systems (DEDSs) are commonly modelled by means of Petri nets (PNs). PNs have the capability to model behaviours such as concurrency, synchronization, and resource sharing, compared to a GRAphe Fonctionnel de Commande Etape Transition (GRAFCET) which is a particular case of a PN. However, there is not a systematic way to implement a PN in a programmable logic controller (PLC), and so it is very common the implementation of such a controller outside a PLC, in some external software that will communicate with the PLC. There have been some attempts to implement PNs within a PLC, but they are dependent on how the logic of places and transitions is programmed for each application. This work proposes a novel application-independent and platform-independent PN implementation methodology. This methodology is a systematic way to implement a PN controller within industrial PLCs. A great portion of the code will be validated automatically prior to PLC implementation. Net structure and marking evolution will be checked on the basis of PN model structural analysis, and only net interpretation will be manually coded and error-prone. Thus, this methodology represents a systematic and semi-compiled PN implementation method. A use case supported by a digital twin (DT) is shown where the automated solution required by a manufacturing system is carried out and executed in two different devices for portability testing, and the scan cycle periods are compared for both approaches.
ARTICLE | doi:10.20944/preprints202112.0047.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Memristor; memristive grid; maze solving; shortest path; programmable devices.
Online: 3 December 2021 (10:08:55 CET)
In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.
BRIEF REPORT | doi:10.20944/preprints201807.0590.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Field Programmable Gate Array, Flight Control System, and Hardware Design.
Online: 30 July 2018 (14:45:25 CEST)
Abstract— Flight Control System is an integrated avionics system equipped with the minimum required components for an autonomous flight. This paper focuses on the Hardware Design of the Flight Control System and presents specific details of the components and its interface. The system architecture is based on Field Programmable Gate Array and Digital Signal Processor. Employing these two processors in the flight control system would improve the Flight Control System performance in terms of fast sequential processing of high-level control algorithms. In addition to Field Programmable Gate Array and Digital Signal Processor, the flight control computer system will also make use of Global Positioning System and Micro Electro Mechanical System sensors. The project will be implemented using Altera’s System On Programmable Chip builder, currently known as Qsys – Platform Designer implemented in Quartus-II. The system employs Nios-II processor which is 32-bit soft-core embedded-processor architecture designed especially for the Altera’s family of Field Programmable Gate Array. From conceptualization to final design, this paper presents the functionality of the different modulus and complex interfaces employed in this Flight Control System.
ARTICLE | doi:10.20944/preprints201806.0393.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: reconfigurable architecture; CORDIC; Field Programmable Gate Array(FPGA); SAR imaging
Online: 25 June 2018 (14:42:01 CEST)
This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.
ARTICLE | doi:10.20944/preprints201810.0325.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Dust Accumulation; Human Machine Interface (HMI); Programmable Logic Controller (PLC); Soiling
Online: 15 October 2018 (16:36:34 CEST)
Solar Energy has enormous potential to fulfill the energy requirements of the world and can be extracted using solar cells. However, the solar cells are affected by poor efficiency and further affected by wind speed, orientation of the panel, temperature and dust deposition. There are different cleaning technologies devised by many industry experts to clean the solar panels. However, they are facing drawbacks when deployed in the solar farm. An efficient cleaning system, along with an added cooling system must be devised, so that the solar panels must be cleaned and cooled often to maximize the energy production. This paper presents a low-cost, energy-efficient, smart and innovative dust cleaning and cooling system for Photovoltaic (PV) Panels. The system is designed, fabricated, fully-automated using Programmable Logic Controller (PLC) and tested successfully. A battery-charging kiosk, capable of charging two, 24V Lead Acid Batteries embedded within this prototype, shall provide clean-energy in a sustainable manner to the rural communities of the developing nations. The user can check the status of the battery such as battery voltage, battery temperature, and state of charge on the Human Machine Interface (HMI) panel while charging the batteries
ARTICLE | doi:10.20944/preprints201806.0138.v1
Subject: Mathematics & Computer Science, Information Technology & Data Management Keywords: controller; industry network; open flow; software defined networking; programmable logic controller
Online: 8 June 2018 (13:35:22 CEST)
Trends such as Industrial Internet of Things (IIoT) and Industry 4.0 have increased the need to use powerfull network technologies in industrial automation. The growing communication in industrial automation is harnessing the productivity and efficiency of manufacturing and process automation with minimum human intervention. Due to the ongoing evolution of industrial networks from Fieldbus technologies to Ethernet, the new opportunity has emerged to integrate the Software Defined Networking (SDN) technique. In this paper, we provide a brief overview of SDN in the domain of industrial automation. We propose a network architecture called Software Defined Industrial Automation Network (SDIAN), with the objective of improving network scalability and efficiency. To match the specific considerations and requirements of having a deterministic system in an industrial network, we propose two solutions for flow creation: Pro-active Flow Installation Scheme (PFIS) and Hybrid Flow-Installation Scheme (HFIS). We analytically quantify the proposed solutions in alleviating the overhead incurred from the flow setup cost. The analytical model is verified through monte carlo simulations. We also evaluate the SDIAN architecture and analyze the network performance of the modified topology using an emulator called Mininet. We further list and motivate SDIAN features and in particular report on an experimental food processing plant demonstration featuring Raspberry PIs (RPIs) instead of traditional Programmable Logic Controllers (PLCs). Our demonstration exemplifies the characteristics of SDIAN.
ARTICLE | doi:10.20944/preprints201708.0019.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Bioimpedance Spectroscopy; Field Programmable Gate Array; Digital Auto Balance Bridge; Multichannel data acquisition;
Online: 4 August 2017 (16:05:29 CEST)
This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.
ARTICLE | doi:10.20944/preprints202201.0399.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Shared Autonomous Vehicle (SAV); Field-Programmable Gate Array (FPGA); Microphone Array; Sound Source Localization
Online: 26 January 2022 (13:07:39 CET)
With the current technological transformation in the automotive industry, autonomous vehicles are getting closer to the Society of Automative Engineers (SAE) automation level 5. This level corresponds to the full vehicle automation, where the driving system autonomously monitors and navigates the environment. With SAE-level 5, the concept of a Shared Autonomous Vehicle (SAV) will soon become a reality and mainstream. The main purpose of an SAV is to allow unrelated passengers to share an autonomous vehicle without a driver/moderator inside the shared space. However, to ensure their safety and well-being until they reach their final destination, it is required an active monitoring of all passengers. In this context, this article presents a microphone-based sensor system that is able to localize sound events inside an SAV. The solution is composed of a Micro-Electro-Mechanical System (MEMS) microphone array with a circular geometry connected to an embedded processing platform that resorts to Field-Programmable Gate Array (FPGA) technology to successfully process in hardware the sound localization algorithms.
ARTICLE | doi:10.20944/preprints202101.0250.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: elliptic curves cryptography (ECC); high speed implementation; unified; Montgomery multiplication; field-programmable gate array (FPGA)
Online: 13 January 2021 (13:03:15 CET)
In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.
ARTICLE | doi:10.20944/preprints201907.0324.v1
Subject: Engineering, Control & Systems Engineering Keywords: motion sensors; seismic sensing; Wadati method; earthquakes; programmable; simulation; test bench; calibration; machine learning; IoT platform
Online: 29 July 2019 (03:11:41 CEST)
Natural calamities observation, study and simulation has always been a prime concern for disaster management agencies. Billions of dollars are spent annually to explore geo-seismic movements especially earthquakes but it has always been a unique accident. The real-time study of seismic waves, ground motions, and earthquakes always needed a programmable mechanical structure capable of physically producing the identical geo-seismic motions with seismology domain definitions. A programmable multi-parametric five degrees of freedom electromechanical seismic wave events simulation platform to study and experiment seismic waves and earthquakes realization in the form of geo-mechanic ground motions is exhibited in this work. The proposed platform was programmed and interfaced through an IoT cloud-based Web application. The geo-mechanics was tested in the range of i) frequencies of extreme seismic waves from 0.1Hz to 178Hz; ii) terrestrial inclinations from -10.000° to 10.000°; iii) velocities of 1km/s to 25km/s iv) variable arrival times 1us to 3000ms; v) magnitudes M1.0 to M10.0 earthquake; vi) epi-central and hypo-central distances of 290+ and 350+ kilometers. Wadati and triangulation methods have been used for entire platform dynamics design and implementation as one of key contributions in this work. This platform is as an enabler for a variety of applications such as training self-balancing and calibrating seismic-resistant designs and structures in addition to studying and testing seismic detection devices as well as motion detection sensors. Nevertheless, it serves as an adequate training colossus for machine learning algorithms and event management expert systems.
ARTICLE | doi:10.20944/preprints202010.0043.v1
Subject: Mathematics & Computer Science, Algebra & Number Theory Keywords: digital device; finite state machine with datapath; algorithm state machine with datapath; field programmable gate array; design technique; development time; reliability; area; performance
Online: 2 October 2020 (13:54:34 CEST)
Recently, there has been, on the one hand, an increase in the complexity of digital device designs and, on the other hand, an increase in the requirements for the development time and the reliability of the designs. One of the directions of solving this problem is developing new techniques for designing digital devices.This paper proposes a new technique for designing digital devices based on finite state machines with datapath (FSMD), when the functioning of the device is described in the form of an algorithm state machine with datapath (ASMD) charts. The new technique is called ASMD-FSMD. Different digital device design techniques are compared to each other using design examples of a synchronous multiplier on field programmable gate array (FPGA). The efficiency of the ASMD-FSMD technique compared to the traditional approach in terms of area and performance was investigated. The ASMD-FSMD technique, compared to the traditional one, reduces the area from 28.6% to 39.7% and increases the speed for some designs to 17.6%. In addition, using the ASMD-FSMD technique significantly reduces design time and increases design reliability. In conclusion, recommendations for using the ASMD-FSMD technique are made.
ARTICLE | doi:10.20944/preprints201810.0049.v1
Subject: Engineering, Biomedical & Chemical Engineering Keywords: Chronoamperometry, Potential Sweep Methods, Reconfigurable Embedded Potentiostat, Portable Potentiostat, Programmable-System-on-a-Chip, Wireless electronics, Smart Instrumentation, Electrochemical low current detection, slave-master setup
Online: 3 October 2018 (13:03:40 CEST)
Under the main features required on portable devices in electrochemical instrumentation is to have a small size, low power consumption, economically affordable, and precision in the measurements. This paper describes the development of a programmable Embedded Potentiostat System (EPS) capable of performing electrochemical sensing over system-on-a-chip platforms. Furthermore, the study explains a circuit design and develops some validation of the entire system. The hardware validation is performed by electrochemical experiments such as Double Step Chronoamperometry (DSC), Linear Sweep Voltammetry (LSV) and Cyclic Voltammetry (CV); moreover, a comparison of the experimental signals between a commercial potentiostat and the EPS was done by analysis of errors on the response signal. Results illustrate that the EPS is capable of handling currents in the range of absolute values of 86.44 to 3000 nA, and having control voltages in the range of ± 2 V. The device can support from 50 to 2000 samples per second. The EPS capabilities were compared with other compact potentiostats. The programmable EPS is an original approach which hugely reduces the hardware complexity and leads the way to create new applications for Point-of-Care or industrial developments with a reusable full electronics module.
ARTICLE | doi:10.20944/preprints201702.0050.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Digital Lock-in Amplifier (DLIA); Field Programmable Gate Array (FPGA); Near Infrared Spectroscopy (NIRS); Hardware Description Language (HDL); Light Emitting Diode (LED); Silicon Photomultiplier (SiPM); Microprocessors
Online: 14 February 2017 (09:11:38 CET)
Functional Near Infrared Spectroscopy (fNIRS) systems for e-health applications usually suffer of poor signal detection mainly due to a low end-to-end signal to noise ratio of the electronics chain. Lock-In Amplifiers (LIA) historically represent a powerful technique helping to improve performances in such circumstances. In this work it has been designed and implemented a digital LIA system, based on a Zynq® Field Programmable Gate Array (FPGA), trying to explore if this technique might improve fNIRS system performances. More broadly, FPGA based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and it has been evaluated its impact on the final signal detection and noise rejection capability. The realized architecture was a mixed solution between VHDL hardware modules and software ones, running within a softcore microprocessor. Experimental results have shown the goodness of the proposed solutions and comparative details among different implementation will be detailed. Finally a key aspect taken into account throughout the design was its modularity, allowing an ease increase of the input channels while avoiding the growth of the design cost of the electronics system.