The problem of health status prediction of insulated-gate bipolar transistors (IGBTs) gains a lot of attention in the field of health management of power electronic equipment. The performance degradation of IGBT gate oxide layer is one of the important failure modes. In view of failure mechanism analysis and easy implementation of monitoring circuit, this paper selects the gate leakage current of IGBT as the precursor parameter of gate oxide degradation, and uses time domain characteristic analysis, gray correlation degree, Mahalanobis distance, Kalman filter and other methods to carry out feature selection and fusion, and finally obtains a health indicator characterizing the degradation of IGBT gate oxide. Based on the Convolutional Neural Network and Long Short-Term Memory (CNN-LSTM) network, this paper constructs an IGBT gate oxide degradation prediction model, and performs experimental analysis on the dataset released by NASA-Ames Laboratory, and the average absolute error of performance degradation prediction is as low as 0.0216. Compared with Long Short-Term Memory (LSTM), Convolutional Neural Network (CNN), Support Vector Regression (SVR) and CNN-LSTM models, CNN-LSTM network has the highest prediction accuracy. These results show the feasibility of gate leakage current as a precursor parameter of IGBT gate oxide layer failure, as well as the accuracy and reliability of the CNN-LSTM prediction model.

Video behavior recognition often needs to focus on object motion processes. In this work, a self-organizing computational system oriented to behavioral clustering recognition is proposed, which achieves the extraction of motion change patterns by binary encoding and completes motion pattern summarization using a similarity comparison algorithm. And in the face of unknown behavioral video data, a self-organizing structure with layer-by-layer accuracy progression is used to achieve motion law summarization by using a multi-layer agent design approach. Finally, the real-time feasibility is verified in the prototype system using real scenes to provide a new feasible solution for unsupervised behavior recognition and space-time scenes.

An orthogonal pore ('orthopore') is conceptually based on an electrolytic cell with a standard pore (the main or 'longitudinal' pore) between cis and trans compartments filled with electrolyte and augmented by a secondary or 'transverse' pore in the form of a channel that is perpendicular to and intersects the main pore. Orthopores can be designed at different scales: macro through micro to nano. With nano-sized pores an analyte (polymer) can be threaded through the main pore and exposed at the junction to electrolyte flow through the secondary pore. Polymer translocation speeds are then independent of the current measured, which can be of an arbitrary magnitude even with the polymer stationary. Orthopores have a wide range of potential applications, including polymer (DNA and protein) sequencing, DNA unzipping, logic circuitry, and protein identification. The present report shows how orthopores can be used to implement boolean logic.

This study introduces a gate design that uses pass transistor switches and enables the implementation of all nec- necessary logic gates with a single structure. This gate design can be used for efficient circuit resizing and creating secure obfuscated circuits. This work also presents simulation results that demonstrate the effectiveness of the gate in performing various logic gate operations.

We report the electrical properties of Al0.3Ga0.7N/GaN heterojunction field effect transistor (HFET) structures with a Ga2O3 passivation layer grown by metal-organic chemical vapor deposition (MOCVD). In this study, three different thicknesses of Ga2O3 dielectric layers were grown on Al0.3Ga0.7N/GaN structures leading to metal-oxide-semiconductor-HFET or MOSHFET structures. X-ray diffraction (XRD) showed the (¯201) orientation peaks of -Ga2O3 in the device structure. The van der Pauw and Hall measurements yield the electron density of ~ 4 x1018 cm-3 and mobility of ~770 cm2V-1s-1 in the 2-dimensional electron gas (2DEG) channel at room temperature. Capacitance-voltage (C-V) measurement for the on-state 2DEG density for the MOSHFET structure was found to be of the order of ~1.5 x1013 cm-2. The thickness of the Ga2O3 layer was inversely related to the threshold voltage and the on-state capacitance. The interface charge density between the oxide and Al0.3Ga0.7N barrier layer was found to be of the order of ~1012 cm2eV-1. The annealing at 900° C of the MOSHFET structures revealed that the Ga2O3 layer was thermally stable at high temperatures resulting in insignificant threshold voltage shifts for annealed samples with respect to as-deposited (unannealed) structures. Our results show that the MOCVD-gown Ga2O3 dielectric layers can be a strong candidate for stable high-power devices.

(1) Background: After the discovery and application of Chlamydomonas reinhardtii channelrhodopsins, the optogenetic toolbox has been greatly expanded with engineered and newly discovered natural channelrhodopsins. However, channelrhodopsins of higher Ca2+ conductance or more specific ion permeability are still in demand. (2) Methods: In this study, we mutated the conserved aspartate of the transmembrane helix 4 (TM4) within Chronos (Stigeoclonium helveticum channelrhodopsin = ShChR) and PsChR (Platymonas subcordiformis channelrhodopsin) and compared them with published ChR2 (C. reinhardtii channelrhodopsin-2) aspartate mutants. (3) Results: We found that the ChR2 D156H mutant (XXM) showed enhanced Na+ and Ca2+ conductance, which was not noticed before, while the D156C mutation (XXL) influenced the Na+ and Ca2+ conductance only slightly. Furthermore, the D173H mutant of PsChR showed a much improved photocurrent, compared to wildtype, and even higher Na+ selectivity to H+ than XXM. PsChR D173H also showed a strongly enhanced Ca2+ conductance, more than 2-fold that of the calcium translocating L132C of ChR2 (CatCh). (4) Conclusions: We found that mutating the aspartate of the TM4 to histidine influences the ion selectivity of channelrhodopsins. With the large photocurrent and enhanced Na+ selectivity and Ca2+ conductance, XXM and PsChR D139H are promising powerful optogenetic tools, especially for Ca2+ manipulation.

A vehicle boom barrier gate system is one of the recently developed technologies operating at the entrances to the restricted areas. This paper aims to design and control of vehicle’s boom barrier gate system using robust augmentation technique. H 2 optimal and H infinity synthesis controllers are used to improve the performance of the system. The open loop response analysis of the vehicle boom barrier gate system shows that the input of the system need to be improved. Comparison of the vehicle boom barrier gate system with H2 optimal and H infinity synthesis controllers have been done to track a set point desired angular position using a step and operational open and close input signals and a promising results have been observed.

In the pursuit of energy-efficient spiking neural network (SNN) hardware, synaptic devices lev-eraging emerging memory technologies hold significant promise. This study investigates the ap-plication of the recently proposed HfO2/SiO2-based interface dipole modulation (IDM) memory for synaptic spike timing-dependent plasticity (STDP) learning. Firstly, through pulse measure-ments of IDM metal-oxide-semiconductor (MOS) capacitors, we demonstrate that IDM exhibits an inherently nonlinear and near-symmetric response. Secondly, we discuss the drain current re-sponse of a field-effect transistor (FET) incorporating a multi-stack IDM structure, revealing its nonlinear and asymmetric pulse response, and suggest that the degree of the asymmetry depends on the modulation current ratio. Thirdly, to emulate synaptic STDP behavior, we implement dou-ble-pulse-controlled drain current modulation of IDMFET using a simple bipolar rectangular pulse. Additionally, we propose a double-pulse-controlled synaptic depression that is valuable for optimizing STDP-based unsupervised learning. Integrating the pulse response characteristics of IDMFETs into a two-layer SNN system for synaptic weight updates, we assess training and classification performance on handwritten digits. Our results demonstrate that ID-MFET-based synaptic devices can achieve classification accuracy comparable to previously re-ported simulation-based results.

With the proportional reduction of MOSFET size, the leakage-to-barrier reduction (DIBL) effect leads to a more significant increase in the tunneling current on the gate, and the appearance of the gate tunneling current also seriously affects the static characteristics of the device. In this paper, a new theoretical model of the relationship between the direct tunneling current and the thickness of the oxide layer under the DIBL effect is proposed for the MOSFET device with ultra-thin oxide layer. On this basis, the characteristics of the MOSFET device are studied in detail by using HSPICE, and their working conditions are quantitatively analyzed. The characteristic variation trend of small-size devices under the influence of gate tunneling current is predicted. The simulation results using BSIM4 model are consistent with the theoretical model. The theory and data in this paper will provide useful reference for large scale integrated circuit design.

The article presents the results of tests related to failure analysis and finding ways to diagnose used semiconductor elements, among other, in power electronics converter systems on vessels and offshore facilities (drilling and production rigs, wind turbines). Diagnostic relationships were found between the temperature change in the above systems and the signals generated in form of elastic waves of acoustic emission.

Abstract— Flight Control System is an integrated avionics system equipped with the minimum required components for an autonomous flight. This paper focuses on the Hardware Design of the Flight Control System and presents specific details of the components and its interface. The system architecture is based on Field Programmable Gate Array and Digital Signal Processor. Employing these two processors in the flight control system would improve the Flight Control System performance in terms of fast sequential processing of high-level control algorithms. In addition to Field Programmable Gate Array and Digital Signal Processor, the flight control computer system will also make use of Global Positioning System and Micro Electro Mechanical System sensors. The project will be implemented using Altera’s System On Programmable Chip builder, currently known as Qsys – Platform Designer implemented in Quartus-II. The system employs Nios-II processor which is 32-bit soft-core embedded-processor architecture designed especially for the Altera’s family of Field Programmable Gate Array. From conceptualization to final design, this paper presents the functionality of the different modulus and complex interfaces employed in this Flight Control System.

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

To study the influence of electrothermal effect of ESD protection device on the reliability of inte-grated circuit,a theoretical model of ESD protection device thermal resistance is constructed in the paper based on the Conservation of Energy Principle. By analyzing the temperature relativity between electricity parameter and thermology parameter of ESD protection device characterized by self-heating thermal resistance, the quantitative relationship expression of physical parameter and geometric parameter is obtained, which can be used to improve ESD protection device elec-tro-thermal effect. The simulation testing and the real tape-out testing of ESD protection device self-heating thermal resistance based on ggNMOS are shown and compared. It is concluded that self-heating thermal resistance is an effective index for the protection device electrothermal char-acterization. Based on the established model, the self-heating thermal resistance could be decreased to improve the homogeneity of the heat transference. The uneven distribution of device temperature can be reduced, and the overall reliability of chips can be improved.

A new kind of quantum gates, higher braiding gates, as matrix solutions of the polyadic braid equations (different from the generalized Yang-Baxter equations) is introduced. Such gates lead to another special multiqubit entanglement which can speed up key distribution and accelerate algorithms. Ternary braiding gates acting on three qubit states are studied in details. We also consider exotic noninvertible gates which can be related with qubit loss, and define partial identities (which can be orthogonal), partial unitarity, and partially bounded operators (which can be noninvertible). We define two classes of matrices, star and circle ones, such that the magic matrices (connected with the Cartan decomposition) belong to the star class. The general algebraic structure of the introduced classes is described in terms of semigroups, ternary and $5$-ary groups and modules. The higher braid group and its representation by the higher braid operators are given. Finally, we show, that for each multiqubit state there exist higher braiding gates which are not entangling, and the concrete conditions to be non-entangling are given for the obtained binary and ternary gates.

Market channel choice makes important contributions to the incomes and other livelihood attributes among smallholder farmers in developing countries. Often considered from a number of perspectives, the dominant view articulated suggests an advantageous integration into formal market channels. This position is questioned as it has implications for smallholder farmers’ food security and rural incomes. Using a mixed methods approach, the study collected primary data from 174 smallholder farmers and applied both a descriptive and multinomial logit regression model to analyze factors contributing to cocoyam production and market channel choices among respondents in the study area. Findings indicate that financial returns and available markets were key factors in cocoyam production, while amount received was a driver of market channel choice among 89% of respondents who sold directly at farm-gate. Farmers’ age (p=0.044), household size (p=0.043), distance to market (p=0.021), additional income (p=0.017) and amount received (p=0.014) were significant variables (p<.05) in the determinants of market channel choice. The study recommended improving market information provision and strengthening farmer associations which will enable smallholder farmers in rural communities to make informed choices with respect to produce price, access other markets and consolidate their collective market bargaining position.

This paper proposes a novel method for optimizing the Cauer-type thermal network model considering both the temperature influence on the extraction of parameters and the errors caused by the physical structure. In terms of prediction of the transient junction temperature and the steady-state junction temperature, the parameters of conventional Cauer-type are modified, and the general method for estimating junction temperature is studied by using the adaptive thermal network model. The results show that junction temperature estimated by adaptive Cauer-type thermal network model is more accurate than that of the conventional model.

Crystalline silicon nanomembrane (Si NM) is promising in wearable and implantable bioelectronics due to its electrical and mechanical performances. However, the current explorations are not enough to firmly bridge ultrathin encapsulation strategies with high performance crystalline Si NM based transistors. In this work, we utilized Al2O3/alucone as the ultrathin encapsulation strategies aim to thoroughly investigate the effect of gate dielectric surface area on the electrical performance of crystalline Si NM based metal-oxide-semiconductor capacitors (MOSCAPs). The comparative analysis was implemented on the three types of diameters (Ø) MOSCAPs with and without Al2O3/alucone encapsulation under planar and concave/convex bending conditions. Benefited from the Al2O3/alucone ultrathin encapsulations, the stability of gate leakage current density, and interfacial characteristics were maintained and improved under mechanical bending deformations for MOSCAPs with predefined Ø of 160, 240, and 320 μm compared to the bare MOSCAPs. Combined with the Ø-related mechanical analysis on the maximum strain in the critical layers and the practical measurements, the encapsulated MOSCAPs with Ø 160 μm showed the most stable electro-mechanical performances. The variations for encapsulated MOSCAPs with three types of Ø emerged in the oxide layer and the interface at dielectric/Si NM that were carefully evaluated according to the bending deformations. These findings are significant for leveraging the practical applications in the ultrathin encapsulation strategies for reliable operations of crystalline Si NM based integrated circuits (ICs).

This work is devoted to the construction and study of commutative gates for a two-qubit quantum system. Using four-dimensional algebra developed by the Kazakh mathematician Abenov M.M. all groups of commutative gates have been constructed, and among all states of a two-qubit quantum system, unitary states with which a specific gate is connected have been identified. An explicit type of gate is described that transfers a quantum system from one unitary state to another unitary state. The proposed approach opens up new possibilities for the design of quantum algorithms not only for two-qubit quantum systems, but also for $n$-qubit quantum systems.

In this paper, the single event burnout(SEB) and reinforcement structure of 1200V SiC MOSFET (SG-SBD-MOSFET) with split gate and schottky barrier diode(SBD) embedded were studied. The device structure was established using Sentaurus TCAD, and the transient current changes of single event effect(SEE), SEB threshold voltage, as well as the regularity of electricfield peak distribution transfer were studied when heavy ions were incident from different regions of the device. Based on SEE analysis of new structural device, two reinforcement structure designs for SEB resistance were studied, namely the expansion of P+body contact area and the design of multi-layer N-type interval buffer layer. Firstly, two reinforcement schemes for SEB were analyzed separately, and then comprehensive design and analysis were carried out. The results showed that the SEB threshold voltage of heavy ions incident from the N+source region was increased by 16% when using the P+body contact area extension alone; When the device is reinforced with multi-layer N-type interval buffer layer alone, the SEB threshold voltage increases by 29%; The comprehensive use of P+body contact area expansion and multi-layer N-type interval buffer layer reinforcement increased the SEB threshold voltage by 33%. Overall, the breakdown voltage of the reinforced device decreased from 1632.935V to 1403.135V, which can be seen as reducing the remaining redundant voltage to 19%. The device performance was not significantly affected.

This paper presents a Modified Gate Diffusion Input (MGDI) design with four inputs for Quantum-dot Cellular Automata (QCA) technology. QCA is a promising nanotechnology that offers benefits such as low power consumption, and high density, making it a potential alternative to CMOS technology. The proposed planar cell design has advantages over previous designs, including a 19% reduction in the number of cells, a 29% reduction in total energy consumption, and a 44% reduction in average energy loss at the same occupancy level. The proposed block is capable of implementing 21 basic combinational functions and various sequential functions. The simulation of functions in 18nm technology and energy consumption calculation indicates that the resulting circuits have improvements of 41%, 27%, 27%, and 20% compared to multiplexers, comparators, four-bit parity circuits, and single-bit memory, respectively. Additionally, the number of cells in the proposed circuits has improved by 10%, 7%, 22%, and 19%, respectively.

The status of vegetation and the impacts of mammalian herbivores on rangelands are complex, and such studies in Kenya are scanty. We investigated the dynamics of ground cover vegetation in Hell’s Gate National Park in relation to mammalian herbivory. Removal of palatable vegetation is postulated to enhance the development of invasive plant species. We investigated the influence of mammalian herbivores on vegetation diversity and dynamics in this rangeland. Three sampling blocks approximately 3 Km apart measuring 100 m x 50 m were established, each divided into three belt-transects (100 m x 10 m), and separated by a 10 m buffer zone. 2 m by 2 m quadrats at 20 m intervals were established in each transect. We measured composition the richness of plant and mammal species, and herbivory levels four times for six months (September 2018 to February 2019). Plant cover (P&lt; 0.001) and species diversity (P&lt; 0.001) differed significantly among sampling blocks and between seasons (P&lt; 0.001). Non-metric multidimensional scaling of plant species and herbivores showed co-occurrence of Zebras with Sida tenuicarpa and giraffes with Solanum incunum. We conclude that the removal of preferred plants through herbivory may be giving an edge to invasive species in the park.

The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios

Two opposed p–n diodes are connected with another junction that causes cancellation of the electric field in the depletion layer of each diode by the field of the other diode. This derived quantum diode is called the A system. Another dual diode, constructed by the same process but with the p- and n-types positioned as duality, called the B system. When a bias voltage is applied between the A and B systems, Lorentz conservation imparts a momentum (i.e., a wave number) to the carriers in the absence of any internal voltage. Thus, a superconducting bias current density appears without the need for cooling. The reappearances of electron–hole pairs on the junction surfaces are assumed to be described by entire wavefunctions normalized by the band gap. Based on the bias superconducting current, NOT and NAND gates were constructed from the quantum diode systems. Numerical calculations revealed that the constant phases of the entire wavefunctions of the p-and n-types converged. Accordingly, it was clarified that Bose–Einstein condensation and the Meissner effect (described by the London equation) occurred in the quantum diode systems. Moreover, the systems exhibited rectification characteristics and a switching speed of the order of 10^-14 s. Combining this switching property with the large bias superconducting current (of the order of several V), we developed NOT and NAND gates with direct quantum correlations among many qubits, which are unaffected by random and thermal noises. These gates have memorization and initialization properties and are compatible with existing and accumulating programing algorithms. Moreover, when harvesting a divergent current output from these systems, the bias superconducting current and memorization property preserve the formed quantum correlations.

Few switching transitions in high power and medium voltage application of Power converters are desirable. The selective harmonics elimination (SHE) pulse width modulation offers a better quality waveform with lower switching transitions and hence lower switching losses. The SHE is a pre-programmed modulation technique where certain amounts of lower order harmonics are removed and fundamental voltage is controlled. After Fourier analysis of output waveform, a set of nonlinear transcendental equations is obtained which exhibits, multiple, unique or no solution in different range of modulation index (MI). In this paper, an iterative method based on the Jacobian estimate is proposed to solve a highly non-linear set of SHE equations. The proposed technique is easy in implementation and can solve a large number of such equations as computation of the Jacobian matrix in the subsequent iteration is estimated from the previous values. Moreover, the proposed method also removes the singularity problem, especially for large SHE equations. High accuracy in the initial guess is also not essential for this method and can converge to the solution with any random initial guess. The computational and simulation results are given to validate the concept. The hardware result is provided to confirm the computational and simulation results.

This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.

In this paper, we study the effect of parasitic channel on electrical characteristics and power consumptions of vertically stacked gate-all-around (GAA) silicon nanosheet (NS) MOSFETs of the bulk and silicon-on-insulator (SOI) substrates. Through deliberate control of the bottom parasitic channel coverage, we systematically assess its influence on DC, AC, and RF characteristics including power consumption. The observed findings highlight a significant differentiation among the bottom parasitic channels: GAA (i.e., control sample with 100% coverage), omega-shaped gate NS (70% and 80% coverages), and FinFET (60% coverage). Compared with the device with a 60% coverage channel, the device with a 100% coverage channel possesses 3520% and 8030% normalized leakage current improvement for both NFET and PFET under the bulk substrate, respectively. Compared with bulk-substrate devices, the SOI-substrate devices further significantly improve the leakage current. Due to enhanced off-state current leakages in the 100% covered bulk-substrate device, the static power demonstrates a notable improvement (about 98.1%), compared to 60% covered devices. Hence, the utilization of a 60% covered channel will result in a degradation of both device and circuit performance. The observation of GAA NS MOSFET indicates that an increase in the bottom parasitic channel coverage ratio leads to a positive impact on power consumption and leakage currents. The examination presented here is useful in the fabrication of stacked GAA NS MOSFETs.

Reliable motor control design is a critical part of the electric vehicle application. Control techniques and motor control devices play an important role in achieving system reliability. In this study, motor control devices have been proposed to implement control techniques in sensorless PMSM. Motor control devices including PWM signal generation by FPGA, gate driver circuit (GDC), and power inverter were developed to be integrated into single-stage motor control devices for sensorless motor control applications. Improvements in GDC design have been the focus to increase the performance of the motor control devices used. Switching losses due to the parasitic elements caused ringing switching behavior of the power inverter circuit, which reduces the performance when the system is integrated. Moreover, in the implementation of sensorless motor control using observer techniques, these conditions affect the accuracy of rotor position estimation, which uses the current or voltage information of the power converter as a variable in the observer design model. Therefore, a GDC design using IR2110 with additional ringing suppression circuit configuration was proposed for the application of motor device control topology to improve the performance of sensorless motor control system. Furthermore, the reduction of switching losses, reduction of current distortion, and accuracy of rotor position information were confirmed by experimental results.

With the current technological transformation in the automotive industry, autonomous vehicles are getting closer to the Society of Automative Engineers (SAE) automation level 5. This level corresponds to the full vehicle automation, where the driving system autonomously monitors and navigates the environment. With SAE-level 5, the concept of a Shared Autonomous Vehicle (SAV) will soon become a reality and mainstream. The main purpose of an SAV is to allow unrelated passengers to share an autonomous vehicle without a driver/moderator inside the shared space. However, to ensure their safety and well-being until they reach their final destination, it is required an active monitoring of all passengers. In this context, this article presents a microphone-based sensor system that is able to localize sound events inside an SAV. The solution is composed of a Micro-Electro-Mechanical System (MEMS) microphone array with a circular geometry connected to an embedded processing platform that resorts to Field-Programmable Gate Array (FPGA) technology to successfully process in hardware the sound localization algorithms.

This work - in two parts - tries to promote a new method in Mathematical Modeling, not ever used before, namely the use of the methods of Non-standard Analysis in Topoi. For the general mathematical theory of topoi (Topoi Theory) we refer to the book [10] . For non-standard analysis in the particular Boolean topos SET (the category of sets) we refer to the book [11]. This first part of the work is related, from an applicative point of view, mainly with Mathematical Neuroscience, more precisely a model of the human thinking, consciousness and subconsciousness. The connections between brain and mind will be also scketched, but a closer study also need some further topics to be studied in Part II: Artificial Intelligence, namely (Quantum) neural networks and (Quantum) Turing machine. However both parts (I. and II.) should be considered together, because they complement each other. The topoi model the intuitionistic logic (multi-valued) and have been used in Quantum Physics (see [9] and its references) while Non-Standard Analysis in SET (introduced by Abraham Robinson[31]) has been applied in Mathematical Economics (see [2] and its references); however, the combination was never used until now in Applied Mathematics. Even more, the Non-standard Analysis in Topoi is not too much studied from the point of view of Pure Mathematics either. One of the main objective of this work is to produce progress in this aria of Mathematics also, mainly for the SET-type topoi and exponential topoi, those topoi used in Quantum Physics and in which we need Non-stantard Analysis for our purposes. Based on the paper [13] we propose the logic of non-standard extensions in topoi as a model of the human thinking (based on infons), these theories representing top and very difficult results in Abstract Mathematics. We will analise the relation between brain and mind via the genetic-epigenetic interplay. More details will be provided in the Introduction, followed by a short presentation of the general theory, later connected with the (Quantum) Yang-Baxter equations in topoi. The connections between these equations and braid groups and knots, with intended applications in Neuroscience and Artificial Intelligence will be further analysed in Part II. Besides promoting a new idea of modeling, the present paper aims to promote the building of a Research Proposal for the European $''$Human Brain Project$''$ (https://www.humanbrainproject.eu/en/), and the NSF-Europe Program $''$Collaborative Research in Computational Neuroscience$''$ (https://www.nsf.gov/funding/pgm\_summ.jsp?pims\_id=5147), jointly with the new founded $''$National Centre for the Research of the Brain$''$ of the Romanian Academy of Science (https://acad.ro/centreAR/CNCC/CNCC.pdf, in Romanian). $''$Blue Brain Project$''$ (https://www.epfl.ch/research/domains/bluebrain/) could also be of big interest. We hope that the journals edited by MDPI (Axioms, in particular) and by the Simion Stoilow Institute of the Romanian Academy - Revue Roumaine de Mathematique Pures et Appliqu (http://imar.ro/journals/Revue\_Mathematique/home\_page.html) - among others - will host special issues related to the research subjects described in both parts of this work, starting with this one. For further details and some of the progress on this research subject, see www.ovidiufpasarescu.com.}

The synthesis and structure of the 4,4′-dipyridyl N,N′-donor ligand with a central thiazolo[5,4-d]thiazole (tztz) unit, named Dptztz is presented. With the linker Dptztz and isophthalate (benzene-1,3-dicarboxylate, 1,3-BDC²⁻) the mixed-linker, two-dimensional coordination network [Zn(1,3-BDC)Dptztz]·DMF could be obtained (DMF = dimethylformamide), which belongs to the class of coordination polymers with interdigitated structures (CIDs). The incorporated DMF solvent molecules can be removed through solvent exchange and evacuation such that the supramolecular 3D packing of the 2D networks retains porosity for CO₂ adsorption in activated [Zn(1,3-BDC)Dptztz]. The first sorption study of a tztz-functionalized porous metal-organic framework material yields a BET surface of 417 m²/g from CO₂ adsorption. The heat of adsorption for CO₂ exhibits a relative maximum with 27.7 kJ/mol at adsorbed CO₂ of about 4 cm³/g STP which is interpreted as a gate-opening effect.

Many advanced technologies have been employed in the high performance active matrix displays including liquid crystal displays, organic light emitting diode displays, and micro light emitting diode displays. On the other side, there have existed the strong demand on the cost reduction and it is one of low cost schemes to integrate the driver circuit in a panel based on thin film transistor technologies. This paper reviews overall concept, operation principles, and various circuit approaches in shift registers for the scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

In the era of the post-quantum Internet of Things (IoT), the implementation of anti-quantum cryptographic algorithms in numerous terminals can successfully defend against prospective quantum computing assaults. Lattice-based cryptography can withstand quantum computing attacks, making it a viable substitute for the currently prevalent classical public-key cryptographic technique. Nevertheless, the algorithm’s significant time complexity will result in a substantial computational burden on the edge computing chip in the IoT terminal. The computation of polynomial multiplication is the most demanding task in lattice-based cryptographic algorithms. Therefore, the investigation into efficient methods for calculating polynomial multiplication is highly important. Quick number theory transformations (NTT) are a widely employed technique to accelerate polynomial multiplication. This study presents a hardware implementation of an efficient number theory transformation. We utilize a multi-level pipeline architecture in the design to accomplish parallel calculations and execute it on a low-profile Artix7-XC7A100T FPGA device. The performance evaluation results demonstrate that our implementation significantly enhances performance and reduces resource usage compared to other existing proposals on the same platform. We suggested NTT core can be implemented in edge computing chips to enhance computational speed due to its small and low-latency design. The experimental results show that the proposed design, which supports both NTT and inverse NTT, achieves 417-Megahertz and consumes only 541-LUTs on Artix-7 XC7A100T.

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Voltage-Temperature-Consumption stable IODELAYS. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and, especially, resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field.

Nowadays, unmanned vehicles are widely used in various fields. However, the safety of unmanned vehicles is directly determined by the autopilot systems, and sensor faults are a very critical factor that affects the normal operation of the autopilot systems. To efficiently and comprehensively test unmanned systems for sensor faults, this paper proposes a chip-level testing platform for unmanned vehicle autopilot systems based on FPGA hardware-in-the-loop simulation. Unlike existing testing platforms, the introduction of FPGA technology allows us to achieve nanosecond real-time simulation frequency, thus realizing chip-level simulation of sensors and black-box automated testing. Firstly, we propose a set of general platform and modeling methods, and the paper presents a detailed application of the four most common necessary sensors in autopilot systems as examples. Secondly, we propose for the first time a chip-level fault testing method for unmanned systems, and build a test platform with a quadrotor vehicle, the PX4 software platform, and the Pixhawk4 hardware platform as examples. Finally, the experimental results verify that the testing platform proposed in this paper can adapt to various autopilot systems and has high simulation test reliability.

The importance and near ubiquity of the Golden Ratio in disciplines like chemistry and biology is well known, but only recently has it come to light in areas pertaining to the Quantum domain. By using a modified tool-kit of hyper-complex numbers (known as Dimensional Gate Operators) and numerical analysis, we uncover a connection between hyper-dimensional objects, the Fibonacci sequence and that of quasiparticles and excitations. The results show that dimensionality increases in step with the Fibonacci sequence.

Recently L-shaped tunneling field-effect-transistor (LTFET) has been introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, shortcoming of LTFET was investigated. It was found that corner effect present in LTFET effectively degrades its subthreshold slope. To get rid of corner effect a new type of device with dual material gates is presented. The new device termed as DG-LTFET gets rid of the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over LTFET. In this work DG-LTFET was evaluated for different device parameters, and bench-marked against LTFET. This work presents an optimum configuration of DG-LTFET in terms of device dimensions and doping levels, to get the best subthreshold, ON current and ambipolar performance from the DG-LTFET.

This paper proposed emotion recognition methods for consecutive facial images, and implements the inference of neural network model on a field-programmable gate array (FPGA). The proposed emotion recognition methods are based on a neural network model architecture that combines convolution neural networks (CNNs), long short-term memory (LSTM), and fully connected neural networks (FCNNs), called CLDNN or ConvLSTM-FCN. This type of neural network mod-el can analyze the local feature sequences obtained through convolution of data, making it suita-ble for processing time-series data such as consecutive facial images. In this paper, sequences of facial images are sampled from videos corresponding to various emotional state of subjects. The sampled images are then pre-processed with the processes includes facial detection, greyscale conversion, resize, and data augmentation if necessary. The 2-D CNN in ConvLSTM-FCN is used for feature extraction for these pre-processed facial images. These sequences of facial im-age features are time sequences with dependent properties between the elements within them. The LSTM is then used to model these time sequences followed by fully connected neural net-works (FCNNs) for classification. The proposed consecutive facial emotion recognition method achieves an average recognition rate of 99.51% on RAVDESS dataset, 87.80% on BAUM-1s dataset and 96.82% on eNTERFACE’05 data set, using 10-fold cross-validation on the PC. Some com-parisons of recognition accuracies between the proposed method and the other existing related works are conducted in this paper. According to the comparisons, the proposed emotion recog-nition methods outperform the existing related researches. The proposed emotion recognition methods are then implemented on an FPGA chip using the neural network model inference algo-rithms in this paper, and the accuracies of the experiments conducted on the FPGA chip are iden-tical to those obtained on the PC. This verifies that the proposed neural network model imple-mented on the FPGA chip performs well.

Iterative Stochastic decoding is an alternative to standard fixed-point decoding of Low-density parity check codes (LDPC) to reduce inter-node routing. In this paper, we propose a Flexible Field-Programmable Gate Array (FPGA)-Based Stochastic decoding (SD) hardware architecture for LDPC codes in the Fifth-Generation (5G) New Radio (NR) Standard that supports decoding of set of various code rates. This decoder’s runtime flexibility is desirable to switch a better performing code rate automatically based on the channel conditions without the extra time needed for reprogramming of FPGA. An offline design method is implemented to generate the hardware description language (HDL) code description of the decoder for the required code-rate set, which is further synthesized and integrated into the Xilinx Kintex-7 series FPGA board to determine the hardware resource utilisation and processing throughput. The Synopsys design tools were employed during both the simulation and synthesis stages, in combination with TSMC 65-nm CMOS standard cell technology, to facilitate comparative analysis. Compared with state-of-the-art designs, the proposed architecture reduces hardware utilization by up to 26% and achieved energy efficiency by 52%.

DNA origami has emerged in recent years as a powerful technique for designing and building 2D and 3D nanostructures. While the breadth of structures that have been produced is impressive, one of the remaining challenges, especially for DNA origami structures intended to carry out useful biomedical tasks in vivo, is to endow them with the ability to detect and respond to molecules of interest. Target molecules may be disease indicators or cell surface receptors, and the responses may include conformational changes leading to release of therapeutically relevant cargo. Nucleic acid aptamers are ideally suited to this task and are beginning to be used in DNA origami designs. In this review we consider examples of uses of DNA aptamers in DNA origami structures and summarise what is currently understood regarding aptamer-origami integration. We review three major roles for aptamers in such applications: protein immobilisation, triggering of structural transformation, and cell targeting. Finally, we consider future perspectives for DNA aptamer integration with DNA origami.

This work implements a stable algorithm in Field-Programmable Gate Arrays (FPGAs) for which two architectures (unrolling the loop) were developed and analyzed. The algorithm recovers sources located at the boundary separating two homogeneous media that make up a two-dimensional non-homogeneous region from measurements on the boundary of such region. The problem of recovering these sources is an ill-posed inverse problem as small errors in the measurement can produce important changes in the source location. Inverse source problems have many applications in different areas, such as engineering and medicine, making the proposed implementation important. The first architecture (mode one) allows considering different operating speeds, which is an advantage depending on whether we work with fast or slow signals. The second one (mode two) reduces resource consumption by exploiting the characteristics of the source identification algorithm, which is an advantage for multichannel problems such as inverse electrocardiography or electroencephalography. The architectures were tested on four FPGAs of the 7 Series of Xilinx: Spartan-7 xc7s100fgga484, Virtex-7 xc7v585tffg1157, Kintex-7 xc7k70tfbg484, and Artix-7 xc7a35tcpg236. The two FPGA implementations of the algorithm were validated using synthetic examples implemented in MATLAB. The results presented here can be extended to concentric spheres and complex geometries.

Recently, there has been, on the one hand, an increase in the complexity of digital device designs and, on the other hand, an increase in the requirements for the development time and the reliability of the designs. One of the directions of solving this problem is developing new techniques for designing digital devices.This paper proposes a new technique for designing digital devices based on finite state machines with datapath (FSMD), when the functioning of the device is described in the form of an algorithm state machine with datapath (ASMD) charts. The new technique is called ASMD-FSMD. Different digital device design techniques are compared to each other using design examples of a synchronous multiplier on field programmable gate array (FPGA). The efficiency of the ASMD-FSMD technique compared to the traditional approach in terms of area and performance was investigated. The ASMD-FSMD technique, compared to the traditional one, reduces the area from 28.6% to 39.7% and increases the speed for some designs to 17.6%. In addition, using the ASMD-FSMD technique significantly reduces design time and increases design reliability. In conclusion, recommendations for using the ASMD-FSMD technique are made.

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi-Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, W-gate MOSFET, and Nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate the ballistic effects and resist the threshold voltage degradation. Besides, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is hence increased to resist the threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. Compared to P-type MOSFET (P-FET), the N-FET shows more threshold voltage because the electron has a more effective mass than the hole

Functional Near Infrared Spectroscopy (fNIRS) systems for e-health applications usually suffer of poor signal detection mainly due to a low end-to-end signal to noise ratio of the electronics chain. Lock-In Amplifiers (LIA) historically represent a powerful technique helping to improve performances in such circumstances. In this work it has been designed and implemented a digital LIA system, based on a Zynq® Field Programmable Gate Array (FPGA), trying to explore if this technique might improve fNIRS system performances. More broadly, FPGA based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and it has been evaluated its impact on the final signal detection and noise rejection capability. The realized architecture was a mixed solution between VHDL hardware modules and software ones, running within a softcore microprocessor. Experimental results have shown the goodness of the proposed solutions and comparative details among different implementation will be detailed. Finally a key aspect taken into account throughout the design was its modularity, allowing an ease increase of the input channels while avoiding the growth of the design cost of the electronics system.

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.