The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.

Vertical-channel organic dual-gate/base transistors would be highly interesting since vertical organic transistors are the fastest organic transistors demonstrated today. However, incorporating a dual gate/base structure into an ultra-short channel vertical architecture represents a substantial challenge. Here, we successfully realize a new device concept of vertical organic permeable dual-base transistors (OPDBTs), where either of both base electrodes can be used to change the on-currents and tune the threshold voltages. The optimized devices yield a high on-current density of 1.54 A cm^-2 and a large current gain of 9.2×10⁵, corresponding to a high transmission value of 99.998%. The detailed operation mechanisms are investigated by calibrated TCAD simulations with the Poole-Frenkel mobility model, Gaussian density of states and tunneling model. Finally, high-performance logic circuits, e.g. inverter, NAND/AND computation functions are demonstrated with one single OPDBT operating at supply voltages of < 2.0 V. We believe that OPDBTs offer a compact and technologically simple hardware platform with excellent application potential for vertical-channel organic transistors in complex logic circuits.

Variations in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. The electric field difference in the circular and spike regions causes nonuniform trapped electron density in the charge trap layer (CTL) and influences the VTH variation. Such less-trapped electron (LT) regions in CTL between the circular and spike regions exhibit a lower electric field during the program, resulting in a higher current flow through that region. For the two-spike cells, the charge distribution and VTH variation are analyzed at different heights (HSpike) and angles between spikes. These irregular cells decrease VTH as the HSpike increases.

Multi-junction solar cells comprised of stacked III-V semiconductor junctions represent the highest-efficiency photovoltaic technology, with recent demonstrations exceeding 47% efficiency . Optimizing the design and thickness of each junction is critical for maximizing performance . This work utilizes Silvaco TCAD tools to systematically optimize a 5-junction cell based on AlInP, AlGaInP, AlGaInAs, GaInP, GaAs, InGaAs, and Ge similar to recent record cells . The junction thicknesses are varied using a predictive profiler to sample the parameter space . For each combination, the spectral absorption and I-V characteristics are simulated to determine the efficiency . Statistical analysis identifies the optimal thickness set that maximizes performance to 26% under 1 sun illumination .