This paper suggests a novel one-dimensional (1D) map to address the limitations of traditional chaotic 1D maps. The main challenge with traditional chaotic 1D maps is the limited control parameter range and the potential risk of collapsing as a result under the finite precision implementation. To overcome these limitations, the new 1D map hybridises the traditional logistic map with tent map, and a linear tent-like function. This hybridization results in a wider range of control parameters to produce chaotic behavior. The dynamic behavior of the new 1D map has been analyzed using well known numerical methods, including the bifurcation diagram and Lyapunov exponent. Both tests have shown their complex and diverse behavior. In addition, a novel image encryption scheme has been devised using the new function as its pseudo-random-number generator. The proposed encryption algorithm has been tested and found to be robust and secure, passing all statistical tests applied to the encrypted images. The results of this study demonstrate the effectiveness of the new 1D map for use in secure image cryptography applications, providing a more robust and secure alternative to traditional chaotic 1D maps. The proposed algorithm has demonstrated high performance in NPCR and UACI tests. It also has shown good results in the MSE and PSNR tests.

Data could be in many forms like text, image, audio, video and many others. Amongst these data, processing image is of important concern even with sophisticated technologies. Generally, images consume more storage space and processing time. This work aims in attaining a novel image encryption strategy that consumes very less computational time with maximum security. The idea is to split the image into blocks and rearrange the pixels in diagonal fashion to achieve confusion. Next, the blocks are combined to form sub images and one block of the sub image is subjected to Secure Hash Algorithm (SHA 512 bits). The SHA bits are XORed with the remaining blocks of the sub image. Finally, the entire image is encrypted using Advanced Encryption Standard (AES). Decryption process is the exact reverse of encryption process. The computational overhead is very low, and security is efficient. The results are compared with existing encryption techniques.

Edge computing has emerged as a significant computing trend alongside the rapid expansion of the Internet of Things (IoT). Computing operations at the network’s edge offer a solution to the high latency and service overload challenges often associated with cloud computing. Additionally, the Secure Hash Algorithm-3 (SHA-3) plays a crucial role in ensuring data integrity and is implemented for numerous applications in the IoT field. Therefore, integrating the SHA-3 accelerator into edge computing is essential. Moreover, recent studies about SHA-3 have primarily focused on achieving high performance and optimizing resource utilization for SHA-3. However, these studies have overlooked the crucial aspect of data transfer between the external memory and the hash function block, as transfer time plays a significant role. This paper proposes an efficient SHA-3 architecture designed for System-on-Chip (SoC) Field Programmable Gate Array (FPGA) to address the aforementioned challenges and be suitable for real edge computing. The architecture contains three key techniques. First, the harmony of padding and Direct Memory Access (DMA) for managing the data transfer process and enhancing performance efficiency based on Serial Input to Parallel Output (SIPO) and a barrel shifter. Secondly, implementing internal pipelining within the Round Function (RF) to reduce critical path delays and optimize resource utilization. Finally, designing four modes (SHA3-224, SHA3-256, SHA3-384, and SHA3-512) to cater to various applications. Our architecture is implemented and tested on the DE10-Standard Development Kit (Cyclone V SX SoC-5CSXFC6D6F31C6N), which is integrated into the FPGA and is controlled by a Dual-Core ARM Cortex-A9 processor. The result is up to 38.34 Gbps in throughput and 5.61 Mbps/ALM in efficiency for the RF computation, 28.02 Gbps in throughput, and 3.63 Mbps/ALM for the full proposed architecture.